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IP / SOC Products Articles

• Case study of a complex video system-on-chip (Dec. 03, 2007)
  The efficient design of complex, multimedia-intensive, heterogeneous multiprocessing (HMP) systems-on-chip (SoCs) for inclusion in HDTVs and related consumer-oriented systems presents a daunting array of challenges. A collaborative effort among IC designers using CoWare's ESL tools and Sonics' SMX smart-interconnect IP designed for this class of SoCs enabled the rapid optimization and verification of the design aspects necessary to meet the critical architectural challenges.
  
  
• Pushing the Frontier in Managing Power in Embedded ASIC or SoC Design with PCI Express (Nov. 26, 2007)
  This paper will discuss some techniques applicable to PCI Express such as changing device power states in coordination with operating system, managing clocks and managing device drivers. In addition, this presentation will present a trade-off analysis between latency and clock frequency with respect to power consumption.
  
  
• Designing a CMOS synthesizer RFIC (Nov. 19, 2007)
  The three major building blocks in a modern, fully-integrated transceiver are a transmitter (TX), a receiver (RX), and a synthesizer. A synthesizer design is quite different from the TX or the RX. Both a TX and a RX have a higher analog content. The synthesizer design has significantly higher digital content. It challenges the designer's analog and digital skills.
  
  
• Using the ARM Cortex-R4 for DSP, part 1: Benchmarks (Nov. 19, 2007)
  BDTI recently completed a benchmark analysis of the ARM Cortex-R4 core and is now releasing the first independent signal processing benchmark results for this processor. In this article, we'll take a look at its benchmark results and compare its performance to that of other ARM cores (including the ARM11, another moderate-performance core) and selected competitors.
  
  
• OCP SoC instrumentation solutions involve more than just trace (Nov. 19, 2007)
  On-chip analysis can effectively improve our understanding of complex embedded systems, such as Open Core Protocol (OCP)-based architectures. For OCP level systems integration, real-time performance analysis is often a priority for getting products to market quickly, and embedded instrumentation analysis that can be used with emulators, prototypes, and production silicon can provide systems information and control that go beyond simulation based analysis
  
  
• Insights using NAND flash in portable designs (Nov. 12, 2007)
  As the raging success of Apple's iPod still rings in our ears, NAND flash memory is seen as the rising star of solid-state memory for portable and consumer applications.
  
  
• Design and implementation of Parallel and Pipelinined Distributive Arithmetic based Discrete Wavelet Transform IP core (Oct. 29, 2007)
  This paper presents an approach towards VLSI implementation of the Discrete Wavelet Transform for image compression. The design follows the JPEG2000 standard and can be used for both lossy and lossless compression. In Discrete Wavelet transform, the filter implementation plays the key role. The poly phase structure is proposed for the filter implementation, which uses the Distributive Arithmetic (DA) technique.
  
  
• Ensuring high-quality video communications (Oct. 22, 2007)
  As the migration to high definition (HD) picks up speed, video system designers are faced with new challenges related to bandwidth requirements, image quality, transcoding and digital media codec flexibility. These are difficult issues even for relatively closed systems that operate in proximity to each other.
  
  
• The Case for DDR-XAUI (Oct. 18, 2007)
  Recent developments in the networking and silicon markets are driving the support of multiple ports of 10 Gigabit Ethernet to the limit. High levels of integration dictate that large numbers of XAUI interfaces must be integrated in silicon to a level where silicon devices are bound by their external interface limitations rather then their internal bandwidth.
  
  
• Design considerations for integrated CMOS receivers (Oct. 15, 2007)
  To meet the demands for the multi-band, multi-mode wireless standards in the current market, a highly integrated wireless receiver (RX) is desired. CMOS technology has become the technology of choice for the integrated receiver design.
  
  
• The RapidIO High-Speed Interconnect: A Technical Overview (Oct. 11, 2007)
  Developers are seeking ways to consolidate interconnect layers across the system. Not only are they trying to more seamlessly connect chips, boards, and chassis, ideally they'd like to collapse the data and control planes into a single fabric.
  
  
• The ARM Cortex-A9 Processors (Oct. 08, 2007)
  This whitepaper describes the details of a newly developed processor design within the common ARM Cortex applications profile
  
  
• 1Tb/s 3W Inductive-Coupling Transceiver IP for 3D-Stacked SiP (Oct. 01, 2007)
  The performance gap between computation in a chip and communication between chips is increasing, making inter-chip communication a bottleneck in development of high-performance LSI systems. One approach to realize high-speed interfaces is to shorten the chip-to-chip distance. System in Package (SiP) reduces the chip-to-chip distance significantly by thinning chips and stacking chips on each other in a package, which provides strong motivation to develop high-speed, low-power, and high-density interface between 3-dimensionally (3-D) stacked chips.
  
  
• Demystifying multithreading and multi-core (Sep. 27, 2007)
  Is multithreading better than multi-core? Is multi-core better than multithreading? The fact is that the best vehicle for a given application might have one, the other or both. Or neither. They are independent (but complementary) design decisions. As multithreaded processors and multi-core chips become the norm, architects and designers of digital systems need to understand their respective attributes, advantages and disadvantages.
  
  
• Employ dynamic power reduction in an ASIC (Sep. 20, 2007)
  Increasing battery life without compromising performance and functionality is a prime concern for the handheld market. The form-factor and economics of this market also demand an ever increasing level of integration for these devices.
  
  
• Cost-effective two-dimensional rank-order filters on FPGAs (Sep. 20, 2007)
  Here's how to use FPGAs as co-, pre-, and post-processing hardware acceleration solutions for video and imaging.
  
  
• A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect (Sep. 10, 2007)
  This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture and an enhanced compiler support for programmability.
  
  
• Ultra-low-power DSP design (Aug. 30, 2007)
  Here's how IMEC built a sub-100uW DSP by tuning its algorithm, processor architecture, and memory system, as well as through clock gating. The article presents detailed power results for each optimization.
  
  
• Analysis: ARC's Configurable Video Subsystems (Aug. 29, 2007)
  Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.
  
  
• Smart InterConnects with Smart IP: Joint Enablers for Rapid MultiMedia SoC Development (Aug. 20, 2007)
  For the past decade, the march of Moore’s “Law” has witnessed the phenomenal growth in System on Chip (SoC) gate counts, allowing the implementation of a confluence of sophisticated algorithms at price points feasible for consumer electronics (e.g., HDTVs, DVD recorders, multi-functional mobile phones, etc.). Unfortunately, gate counts over the past decade have grown far faster than IC designers’ productivity. With so much pressure to launch high end consumer products before prices (and margins) erode, generations change, new standard features are added, and additional competition surfaces, every aspect of the design flow requires analysis to see how, if, when, and where time-to-silicon can be shortened.
  
  
• DSP silicon takes many forms (Aug. 20, 2007)
  Here's a guide to the chips use in signal processing: DSPs, MPUS, FPGAs, multiprocessors, massively parallel processors, and more!
  
  
• IP Core for RAID 6 Hardware Acceleration (Aug. 13, 2007)
  As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures.
  
  
• Overcoming Wireless USB commercialization challenges (Aug. 09, 2007)
  Today, the face of UWB and Wireless USB technology continues to evolve as it marches toward mass market commercialization. Wireless USB, also known as Certified Wireless USB, is a short-range, high-bandwidth wireless extension to USB that combines the speed and ease-of-use of USB 2.0 with the convenience of wireless technology.
  
  
• Designing with proven implementations of the Inter IC bus (Aug. 09, 2007)
  Because the I2C bus is currently the industry's most widely used serial bus, it behooves a system designer to have a handful of proven implementations on hand. The method you choose - on-chip, bit-banged, or IP-core implementation - depends mostly on the system processor, but nothing is easier than using an approach that is proven and already works. This article includes a working reference for each of the three methods.
  
  
• How video compression works (Aug. 06, 2007)
  BDTI explains how video codecs like MPEG-4 and H.264 work, and how they differ from one another. It also explains the demands codecs make on processors.
  
  
• Analysis: Tensilica's D1 Video Engine (Aug. 02, 2007)
  Tensilica is now offering a high-performance licensable video engine capable of MPEG-4 ASP encoding at D1 resolution. The processor is called the Diamond 388VDO, and it's one of four new dual-core "VDO" video engines from Tensilica.
  
  
• Utilizing UWB in ultra-low power ZigBee wireless sensor nodes (Jul. 30, 2007)
  In this article, we discuss some of the key challenges associated to the design of UWB transmitters. We further present the first reported transmitter complying with the new 802.15.4a standard, which has been implemented in standard 90 nm CMOS technology and shows a record low-power consumption of 1 mW for a net data rate of 0.85 Mbps.
  
  
• Self-timed interconnect enables true IP reuse (Jul. 26, 2007)
  Despite many claims from both third-party IP vendors and from internal IP development groups at chip companies that their IP is reusable from design to design with little or no rework or extra verification, this is simply not the case. Since every IP core "sees" a different environment in each unique design that employs it, chip designers have to expend considerable effort on each design to verify the IP's operation within it.
  
  
• Analysis: CEVA's 32-bit, Dual-MAC TeakLite-III DSP (Jul. 26, 2007)
  The TeakLite-III cores build upon CEVA's earlier TeakLite cores, CEVA-TeakLite and CEVA-TeakLite-II, with which the TeakLite-III is backwards compatible. To meet the precision and throughput demands of its intended applications, which include high-end audio, 3G cellular, VoIP, and portable audio players, the TeakLite-III features support for both 32-bit and 16-bit fixed-point data, and increased MAC throughput relative to the earlier TeakLite cores.
  
  
• Compiler optimization for DSP applications (Jul. 23, 2007)
  Smart selection of compilation options can yield a dramatic code performance improvement. For example, code size can be greatly reduced. This is often a major factor when evaluating the cost of a product, as it has a direct influence on the amount of memory required. This article shows how to improve code size consumption as well as the consumption of other important resources.Smart selection of compilation options can yield a dramatic code performance improvement. For example, code size can be greatly reduced. This is often a major factor when evaluating the cost of a product, as it has a direct influence on the amount of memory required. This article shows how to improve code size consumption as well as the consumption of other important resources.