D&R Industry Articles | Most Popular | SoC News Alerts |

IP / SOC Products Articles

• Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2 (Aug. 31, 2009)
  This paper will review the new DDR3 features and compare and contrast them to previous features available in the DDR2 specification. One of the biggest changes is the in Physical Layer (PHY) portion of the memory interface and these changes will be high-lighted and illustrated with an example design of a high performance processor interface. The areas where backwards compatibility should be maintained will also be illustrated with an example design, showing how simple changes can provide significant benefits in re-use and system flexibility.
  
  
• Achieving scalability with switch fabrics in CompactPCI (Jul. 16, 2007)
  The requirements of applications for which embedded systems are being designed vary in complexity, cost and performance widely. Presenting extreme challenges for designers of systems that must support not only a wide range of applications, but a continuously changing set of performance requirements.
  
  
• 3D graphics hardware IP uses OCP bus interface (Jul. 16, 2007)
  Providing scalable high performance low power 3D graphics cores to the embedded space for handheld devices, mobile phones, vehicle navigation systems, amusement game consoles and other embedded graphics applications, DMP has adopted the Open Core Protocol as the standard bus interface for their components.
  
  
• FlexRay - The Hardware View (Jul. 12, 2007)
  FlexRay is an upcoming networking standard being established to raise the data rate, reliability, and safety of the automotive applications of today and tomorrow. Synthesizable FlexRay intellectual property (IP) is now available for those who want to integrate it into a new chip. This paper discusses what the FlexRay IP is and how to implement it; highlighting issues, considerations, and solutions for the system designer.
  
  
• Selection Criteria for Using DDR, GDDR or MobileDDR Memories in System Designs (Jul. 09, 2007)
  This paper will include a short review of the key features of DDR, GDDR and MobileDDR memory architectures, covering power, speed and cost characteristics as well as key functionality differences that can impact overall system architecture. Using real system design experiences each of the main memory architectures will be used to address system design challenges of sustained bandwidth, reliability, access priority, power savings, and interface requirements.
  
  
• Fully Digital Implemented Phase Locked Loop (Jul. 05, 2007)
  This paper shows an approach for a PLL that only uses digital cell libraries. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the PLL also can be used in a FPGA. One of the most astonishing feature is the possibility to check the whole functionality with a pure digital simulator. So without an analog simulator like Spice performance values like frequency and jitter can be checked.
  
  
• Data compression tutorial: Part 3 (Jun. 28, 2007)
  Part three of this three-part series explains how JPEG and MPEG compression work.
  
  
• STBus complex interconnect design and verification for a HDTV SoC (Jun. 18, 2007)
  To support High Definition Television (HDTV) application, the System on Chip (SoC) presented in this paper has to support multiple and concurrent internal processes. Most of these operations read data from memory, process them and store the resulting data into memory. Each functional unit of the system is responsible for a specific data processing, but all the data are stored in the same shared external memories.
  
  
• OTP for DCP Key Storage (Jun. 11, 2007)
  Non-volatile storage of encryption keys is an ideal way to securely implement DCP in a variety of electronic devices. However, not all non-volatile memory (NVM) technologies are suited for these applications. This paper will review some available NVM alternatives for DCP-enabled products and describe an innovative logic NVM IP technology that meets the diverse requirements for encryption key storage.
  
  
• Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment (Jun. 07, 2007)
  The ability to design high quality IP and to enable work practices for reuse methodology helps to achieve working SoCs in a timely and efficient manner. This paper describes a methodology for implementing IP reuse practices suited to an academic environmen
  
  
• Video over IP with forward error correction (FEC) (Jun. 04, 2007)
  This low cost Video over IP implementation bridges an MPEG transport stream with an Ethernet-based Internet Protocol network. The design uses real time transport protocol encapsulation, and Pro-MPEG Code of Practice #3 (CoP3) forward error correction
  
  
• How to design an Interlaken to SPI-4.2 bridge (May. 31, 2007)
  The future of networking is about higher bandwidth and lower power. More and more applications, such as video, continue to drive the bandwidth demands placed on networking equipment. At the same time, networking equipment must deliver these higher bandwidths without a dramatic increase in power consumption.
  
  
• RAID6 accelerator in a PowerPC IOP SOC (May. 28, 2007)
  This paper describes a PowerPC system-on-a-chip (SOC) which is intended to address the high-performance RAID market segment. The SOC uses IBM's Core-Connect technology to integrate a rich set of features including a DDRII-800 SDRAM controller, three 2.5Gb/s PCI-Express interfaces, hardware accelerated XOR for RAID 5 and RAID 6, I2O messaging, three DMA controllers, a 1Gb Ethernet port, a parallel peripheral Bus, three UARTs, general purpose IO, general purpose timers, and two IIC buses.
  
  
• Realizing the Performance Potential of a PCI-Express IP (May. 21, 2007)
  This paper describes challenges involved in realizing the maximum performance of a configurable interconnect IP (GPEX - Rambus PCI Express Digital Controller). The following sections describe how various performance metrics such as roundtrip latency and bandwidth can be used to characterize a PCI Express IP performance and its impact on the system. The ideas presented can also be applied to other high speed interconnect architectures like RapidIO and Hypertransport
  
  
• Standard Debug Interface Socket Requirements For OCP-Compliant SoC (May. 21, 2007)
  Debug for SoC adds new requirements and challenges in terms of adding visibility and control to a system, simplifying integration of hardware and software instrumentation into design flows, and supporting emerging needs for architectures incorporating complex network on chip buses, multiple cores, multithreading, embedded security, power management and other issues.
  
  
• Low Power 7T SRAM Cell Scheme - ''Saving Write Zero Power'' (May. 21, 2007)
  This paper presents a Seven-transistor SRAM cell intended for the advanced microprocessor. A low power write scheme, which reduces SRAM power by using seven-transistor sense-amplifying memory cell, has been described. By reducing the bitline swing and amplifying the voltage swing by a sense – amplifier, which is a part of the memory cell, the charging and discharging component bit / data lines power consumption is reduced.
  
  
• Tutorial on 802.11n PHY layer (May. 17, 2007)
  Part 1 of this tutorial covers the history of the IEEE 802.11 standard, the objectives of 802.11n, and how higher data rates are achieved
  
  
• Timing Constraints Generation Technology (May. 17, 2007)
  As design complexity has scaled upward, the need to provide accurate physical constraints like timing, area, power and port locations have become increasingly important. Of these, Timing Constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the total effort to achieve timing closure, but also reduce the number of iterations to achieve that goal.
  
  
• Synthesizable Switching Logic For Network-On-Chip Designs on 90nm Technologies (May. 14, 2007)
  The trend towards more scalable, plug-and-play type of communication architectures has become apparent as SoCs have built up on complexity. However, there is currently no widely accepted on-chip communication mechanism that would offer unlimited scalability. Existing multiprocessor SoCs use hierarchical buses such as AMBA and CoreConnect. Sonics Micronetwork and STBus [4] present a step towards more flexible bus architectures.
  
  
• Anatomy of a hardware video codec (May. 14, 2007)
  Inside the Diamond Video Engine for encoding/decoding H.264/AVC video.
  
  
• Symmetric Cryptographic Offload Options for SoC Designers (May. 10, 2007)
  Encryption requirements are now found in almost every new SoC design. This paper focuses on symmetric offload in a packet processing system for IPsec but the concepts apply equally well to SSL, SRTP and link security.
  
  
• Compression/decompression tradeoffs for data networking and storage (May. 10, 2007)
  Several design trade-offs to exist when building a high performance lossless data compression engine. Each of these trade-offs can vary the gate area of the end design greatly and have significant impact on the overall efficiency of the compressor (compression ratio).
  
  
• Reusable debug infrastructure in multi core SoC : Embedded WiFi case study (May. 07, 2007)
  This paper outlines a system level reusable hardware-software debug infrastructure for a complex multi core SoC and describes how this can be integrated with existing third party debug tools such as ARM MultiIce and logic analyzers. The concepts are illustrated through the case study of multi core multi million gate embedded WiFi project.
  
  
• Analysis: CEVA's ''Lite'' Mobile Multimedia Platform (May. 02, 2007)
  In March CEVA unveiled ''Mobile-Media-Lite'' (MMLite), a family of multimedia processing solutions comprising licensable silicon IP and software. The family is aimed at low-end multimedia-enabled devices such as mobile TV players, portable multimedia players, and multimedia phones.
  
  
• IP Core for an H.264 Decoder SoC (Apr. 30, 2007)
  This paper presents the development of an IP core for an H.264 decoder. This state-of-the-art video compression standard contributes to reduce the huge demand for bandwidth and storage of multimedia applications. The IP is CoreConnect compliant and implements the modules with high performance constraints.
  
  
• How to build ultra-fast floating-point FFTs in FPGAs (Apr. 30, 2007)
  Here's how to build a hybrid fixed/float FFT that achieves gigasample-per-second performance and can scale from 32 to 2,048 points.
  
  
• DPCI: An Efficient Scalable System-on-chip Communication Architecture (Apr. 26, 2007)
  This paper presents an efficient scalable communication architecture, Data Pre-fetch Core Interface (DPCI), for shared-bus based SOC systems to support scalable and pipelining communication between those IP blocks, the shared memory and the bus so as to improve the system performance and increase the system bandwidth and flexibility. The proposed architecture exhibits both hardware simplicity and system performance improvement.
  
  
• Silicon IP for Programmable Baseband Processing (Apr. 23, 2007)
  An efficient IP reuse strategy relies on IP blocks with wide applicability. That makes generic blocks, such as programmable processors preferable. However, in many applications such as handheld wireless terminals, additional silicon area and power consumption compared to fixed function solutions can not be accepted.
  
  
• Unifying Diversity -- A classic example of Reusability (Apr. 19, 2007)
  In pursuit of meeting this objective of integrating resources while first silicon success remains the ultimate goal, several approaches are tried and reusability has emerged as a more comprehensive solution. Different teams, different domains and different locations have with them diversified expertise and methodologies and integrating them is a challenge in itself.
  
  
• Get multicore performance from one core (Apr. 18, 2007)
  System-on-chip (SoC) designers know what it's like to do more with less. They're constantly challenged by ever-increasing constraints on system cost and power consumption while being tasked with increasing the performance and functionality of their designs. The tricks of the trade available to designers are, at best, a set of difficult trade-offs.