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IP / SOC Products Articles

• The value of selecting IP based on a platform (Apr. 16, 2007)
  The platform often includes both software and hardware components. IP suppliers with comprehensive platforms not only provide peace of mind by conveying their application domain expertise, but also provide a true framework that enables design engineers to build end-to-end solutions that meet their needs.
  
  
• A Central Caching Network-on-chip Communication Architecture Design (Apr. 12, 2007)
  This paper presents a new NOC switch architecture which we have called CTCNOC (Central caching NOC) to offer an attractive way to reduce the system area overhead and increase system performance. The head-of-line and deadlock problems have been significantly alleviated. Through experimentation it has been shown that the proposed architecture not only exhibits hardware simplicity, but also increases overall system performance.
  
  
• Deploying Mixed Signal IP -- Is ''No Re-Spin'' Just Spin ? (Apr. 10, 2007)
  One of the key benefits for the customer in the growth of the IP market has been the increasing availability of silicon proven high performance data converters, typically the bottleneck in overall system performance. So has the mixed signal IP business removed the need for the traditional mixed mode SOC re-spin?
  
  
• The Growing Need for Secure Storage in Automotive Systems (Apr. 10, 2007)
  Automotive system memory comes in many different forms, ranging from just a few hundred bits to store IDs and sensor calibration data up to several megabytes to hold complex programs in firmware. Different systems have different requirements for the non-volatile memory (NVM) they use, but all are looking for memory that is inexpensive, reliable, secure and easily implemented in their respective systems.
  
  
• Integrating PCI Express IP in a SoC (Apr. 02, 2007)
  Due to protocol flexibility and the wide range of supported applications, PCI Express IP usually provides extensive configurability options for optimizing the PCI Express solution for the application's needs. This paper elaborates on the PCIe IP parameterization process and provides useful tools for the PCIe solution evaluation, specification, and verification.
  
  
• An Implementation Study on Fault Tolerant LEON-3 Processor System (Mar. 26, 2007)
  The paper presents a case study on implementation of the fault tolerant LEON-3 processor system on a chip for space applications. The single-event upset (SEU) tolerance is provided by design. The technique applied detects and corrects up to 4 errors in the register file and caches. The implementation details and system-on-chip features are summarized.
  
  
• Hardware Implementation of a Combined Interleaver and DeInterleaver (Mar. 19, 2007)
  The implementation of any Wireless Base band system as an IP is complex. One of the key components in the IP is the Interleave / DeInterleave process, which requires a careful implementation to obtain an optimal solution in terms of area and speed. The Interleave / DeInterleave process can consist of multiple stages and the approach of implementing these stages individually is not optimal.
  
  
• How to design a scalable OFDMA engine for WiMAX (Mar. 15, 2007)
  FPGAs deliver a scalable solution for WiMAX that offers flexibility, superior performance and fast time to market.
  
  
• An Overview of Secret Key and Identity Management for System-on-Chip Architects (Mar. 12, 2007)
  The paper begins with a brief overview of techniques for identification and authentication then follows that with a discussion of technical means to implement them in a System-on-Chip (SoC).
  
  
• Advanced interconnects drive intelligent vision applications: Part 1 (Mar. 12, 2007)
  Platform-centric methodology enables decoupling IP cores for parallel engineering with data flow design, early architecture exploration of data flows to characterize processor performance, and isolation of chip areas for rapid re-engineering of derivatives and updates.
  
  
• A High-Performance Platform Architecture for MIPS Processors (Mar. 08, 2007)
  With time-to-market pressures mounting for complex 90nm and 65nm SoCs, MIPS Technologies and its partners can now offer fully verified platform architectures and supporting environments. This presentation will provide insight into a new high-performance platform architecture for MIPS-Based™ SoCs. A key goal is to allow high peak processor performance to be sustained for real-world applications which – unlike Dhrystone– include cache miss, interlock stalls and interrupts.
  
  
• Making your UWB solutions ''Future Proof'' (Mar. 05, 2007)
  New technologies bring with them new opportunities as well as new uncertainties. In order to make best use of technology, one has to be prepared for today as well as for the future. This often involves tradeoffs between current opportunities and future potential. In this article, the effort is to illustrate a possible tradeoff one has to make while developing the solutions based on Ultra Wideband.
  
  
• Which USB is Right for Your Application? (Part 2) (Feb. 22, 2007)
  The release of USB 2.0 enabled high-speed connections. An even greater explosion in the number of available USB peripherals greatly enhanced the end-user experience. Part 1 summarized the evolution of the USB standard. Part 2 addresses common applications and determine which flavor of USB is best for a given application.
  
  
• Developing an automotive electrical distribution system Part 1: System design (Feb. 22, 2007)
  Efficient wiring design is vital to the explosive growth of vehicle electronics, and shorter design cycles
  
  
• Using a Versatile, Independent IP Platform for SoC Design (Feb. 19, 2007)
  This paper shows how companies adopting an IP platform approach can maximize the benefits of their investment by choosing a flexible, versatile platform suitable for a variety of projects. Major points to consider are illustrated through one such platform, the PIP-AMBA from CAST
  
  
• Which version of USB is right for your application? (Part 1) (Feb. 19, 2007)
  The Universal Serial Bus (USB) peripheral interface has become ubiquitous across all personal computing platforms as well as many industrial and infrastructure platforms. However, at the same time, the version of the specification that is right for a given application—USB 1.0, USB 1.1, USB 2.0, On-the-Go (OTG), WirelessUSB (WUSB)—can lead to confusion.
  
  
• Designing low-power multiprocessor chips (Feb. 15, 2007)
  Today, advancements in semiconductor process technologies let designers easily pack millions of gates and complex mixed-signal components into a single chip. Nonetheless, chip designers still face the challenge of reducing the number of gates and implementing efficient architectures--not only to reach a target size but also to reduce total system power consumption.
  
  
• Improve performance and reduce power consumption in mixed-signal designs (Feb. 15, 2007)
  Designing high-reliability satellite communications systems is perhaps the most challenging mixed-signal design task. In addition to withstanding a wide range of temperatures and radiation, these systems also have to offer unprecedented levels of performance and reliability
  
  
• Can the ARM11 handle DSP? (Feb. 15, 2007)
  ARM's general-purpose processor cores have long been used alongside DSP processors in products like cell phones, where the ARM core typically handles tasks like packet processing, user interface, and overall control, and the DSP handles the computationally demanding signal processing. But as ARM has gradually upgraded its cores with DSP-oriented features, more chip and system designers are considering whether to use an ARM core as a DSP engine. The question is, how much signal processing work can an ARM core handle?
  
  
• SoC boosts speech-recognition systems (Feb. 08, 2007)
  To date, the Uni-Speech SoC has shown good performance in accurate speech recognition and low-rate high-quality speech encoding/decoding. However, the economics and power consumption of the current solution limit its potential in portable speech-recognition applications. This opens up opportunities for Uni-Lite, an SoC that addresses cost and power consumption.
  
  
• The challenges of nextgen multicore networks-on-chip systems: Part 1 (Feb. 05, 2007)
  The reason for the growing interest in networks on chips (NoCs) can be explained by looking at the evolution of integrated circuit technology and at the ever-increasing requirements of electronic systems. The integrated microprocessor has been a landmark in the evolution of computing technology.
  
  
• Fully Digital Implemented Phase Locked Loop (Feb. 05, 2007)
  This paper shows an approach for a PLL that only uses digital cell libraries. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the PLL also can be used in a FPGA. One of the most astonishing feature is the possibility to check the whole functionality with a pure digital simulator. So without an analog simulator like Spice performance values like frequency and jitter can be checked.
  
  
• A Security Tagging Scheme for ASIC Designs and Intellectual Property Cores (Jan. 29, 2007)
  This paper introduces a novel idea for labelling and protecting electronic designs and in particular Intellectual Property (IP) Cores, implemented in Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs).
  
  
• Main profile H.264 codec: A low power implementation for consumer applications (Jan. 11, 2007)
  A New Video Compression Standard and its Paradigm
  
  
• Top 10 methods for ASIC power minimization -- Part 2 (Jan. 11, 2007)
  This is the second part of a two part article focusing on power minimization in deep submicron ASICs. The focus of this part is on five effective implementation level low power techniques.
  
  
• Top 10 methods for ASIC power minimization -- Part 1 (Jan. 08, 2007)
  This is a two-part article focusing on power minimization in deep submicron ASICs.
  
  
• DDR Memory Systems at the Heart of Consumer Electronics (Jan. 08, 2007)
  In this article, DDR memory systems will be discussed in the context of consumer electronics design, with an emphasis on the need for a multi-disciplined, system-level approach. A brief look of relevant market pressures are followed by review of key issues in memory system development, including device selection, controller and PHY (Physical) design, and system integration. The article concludes with an example of commercially available solutions that address the key issues.
  
  
• Optimize your DSPs for power and performance (Jan. 04, 2007)
  To get the best balance of power and performance, chip designers need to use a wide range of techniques.
  
  
• Design and Real Time Hardware Implementation of a Generic Fuzzy Logic Controller for a Transport/Diffusion System (Jan. 02, 2007)
  A fuzzy controller design methodology for the control action in the transport/diffusion is presented here. The efficient design of the controller according to the desired specifications using VHDL and its implementation on FPGA introduces a novel approach for realizing a generic prototype of the controller, applicable in real time systems.
  
  
• Extracting value from integrating power-management (Jan. 02, 2007)
  Find out how to get the most from your SoC design for meeting multiple power needs.