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IP / SOC Products Articles

• VESA Video Compression on MIPI DSI-2 Enables Next-Generation Display Applications (Dec. 12, 2022)
  Over the past decade, we have seen generations of new products with increasingly sophisticated display feature sets. Each new generation pushes the boundaries of display technology even further with higher resolutions, faster refresh rates, and increased pixel depth at the forefront of these developments.
  
  
• Is your career at RISK without RISC-V? (Dec. 02, 2022)
  I am delighted to share my technical insights into RISC-V in this article to inspire and prepare the next generation of chip designers for the future of the open era of computing. If you understand how we build complex electronic devices like desktops and smartphones using processors, you would be more interested in learning and exploring the Instruction Set Architectures.
  
  
• Radiation Tolerance is not just for Rocket Scientists: Mitigating Digital Logic Soft Errors in the Terrestrial Environment (Nov. 28, 2022)
  As technology scales, soft errors from particle radiation are becoming increasingly concerning for in-field reliability. These radiation effects are called Single Event Upsets (SEU) and the frequency of the failures due to SEUs is known as the Soft Error Rate (SER). Soft errors are failures due to external sources. By contrast, hard errors refer to actual process manufacturing defects or electromigration defects that get formed during circuit operation.
  
  
• How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power (Nov. 21, 2022)
  Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when the device is not active (leakage power).
  
  
• Efficient Verification of RISC-V processors (Nov. 16, 2022)
  Processor verification, however, is never trivial but requires combining the strengths of multiple verification techniques. This technical paper considers how to efficiently verify a RISC-V processor using a multi-layered approach known as the Swiss cheese model adapted from the world of avionics.
  
  
• Integrating high speed IP at 5nm (Nov. 14, 2022)
  In this article, we will look at the new challenges which have been introduced due to 5nm technology as well due to new additional functionality in SoC. We will show the approach to tackle the floor planning and timing issue to reduce the physical implementation iteration.
  
  
• Put a Data Center in Your Phone! (Nov. 07, 2022)
  Datacenters heavily leverage FPGAs for AI acceleration. Why not do the same for low power edge applications with embedded FPGA (eFPGA)?
  
  
• Driving ADAS Applications with MIPI CSI-2 (Nov. 03, 2022)
  We’re all familiar with seeing social media influencers on our mobile phones these days, but when you think about it, the real influencers are the mobile phones themselves. Over the past decade, as mobiles have evolved and pushed all sorts of technological boundaries, they have influenced other industries to follow suit.
  
  
• Compute Express Link 3.0 (Oct. 24, 2022)
  Compute Express Link™ (CXL™) is an open industry standard interconnect offering high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices.
  
  
• Next-Generation Voice Assisted Solutions (Oct. 17, 2022)
  With the emergence of advanced AI technologies, companies may create synthetic speech that sounds like a human voice to resolve customer queries more effectively. Businesses across a variety of industries, including retail, automotive, media & entertainment, and healthcare, are realising the benefits of the technology and are using it to provide better, and more individualized customer experiences.
  
  
• Arteris System IP Meets Arm Processor IP (Oct. 12, 2022)
  The design of system-on-chip (SoC) devices for automotive applications—and the reuse of portions of those designs for future SoC incarnations—just got a lot easier with the recent announcement of the expanded partnership between Arm and Arteris.
  
  
• O-RAN Fronthaul Security using MACsec (Oct. 10, 2022)
  With 5G being deployed for time-sensitive applications, security is becoming an important consideration. At the same time, Open Radio Access Networks (RAN) are gaining more interest from mobile carriers and governments. Yet, Open RAN networks have serious security challenges, especially in the RAN fronthaul where there are strict timing requirements. This paper proposes MACsec as an efficient data link layer security solution that can assist in meeting these challenges.
  
  
• Interlaken: the ideal high-speed chip-to-chip interface (Sep. 26, 2022)
  As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability.
  
  
• Moving from SoCs to Chiplets could help extend Moore's Law (Sep. 26, 2022)
  As Moore’s Law is again reaching its limits, several technologies, specifically Chiplets, could be the key to extending it for many more years.
  
  
• How to manage changing IP in an evolving SoC design (Sep. 23, 2022)
  IPs undergo multiple revisions due to evolving specifications and managing these changes as the SoC design evolves can become a nightmare.
  
  
• MACsec for Deterministic Ethernet applications (Sep. 19, 2022)
  Why MACsec is a compelling security solution for Deterministic Ethernet networks and how Packaged Intellectual Property solutions can accelerate time-to-market for chip developers
  
  
• Multi Voltage SoC Power Design Technique (Sep. 15, 2022)
  Minimizing power consumption is a major factor that contributes to the modern-day development of IC designs, especially in the consumer electronics segment.
  
  
• What's Really Behind the Adoption of eFPGA? (Sep. 08, 2022)
  System companies are taking a more proactive role in codesigning their hardware and software roadmaps, so it’s no surprise that they are also driving the adoption of embedded FPGAs (eFPGA.). But why and why has it taken so long?
  
  
• How to accelerate memory bandwidth by 50% with ZeroPoint technology (Sep. 05, 2022)
  Digitalization quickly accelerates energy consumption and is projected to stand for more than one-fifth of global electricity demand by 2030. This makes "performance per watt" critical. ZeroPoint technology for microchips delivers up to 50% more performance per watt by removing unnecessary information.
  
  
• eFPGAs Bring a 10X Advantage in Power and Cost (Sep. 02, 2022)
  eFPGA LUTs will out ship FPGA LUTs by the end of the century because of the advantages of reconfigurable logic being built into the chip: cost reduction, lower power and improved performance.
  
  
• Traceability Complements Agile Design (Aug. 29, 2022)
  Agile design methods have become mainstream in software development as traditional waterfall approaches cannot scale in large, fast-moving product schedules. System-on-chip (SoC) development teams have noticed and are enthusiastically adopting similar methods to accelerate schedules and become more nimble to in-process requirement changes.
  
  
• Multi-Die SoCs Gaining Strength with Introduction of UCIe (Aug. 29, 2022)
  The Universal Chiplet Interconnect Express UCIe specification brings together very competitive performance advantages to multi-die system designers, including high energy-efficiency, high edge usage efficiency and low latency, and more. Read this article to learn all about UCIe and its many advantages for multi-die system designs.
  
  
• Implementation basics for autonomous driving vehicles (Aug. 25, 2022)
  A successful AD system implementation rests on a state-machine architecture that can formulate a truthful understanding of the environment, produce an efficient motion plan, and flawlessly perform its execution.
  
  
• What's the Difference Between CXL 1.1 and CXL 2.0? (Aug. 25, 2022)
  Compute Express Link is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices.
  
  
• The case for de-integrating embedded Flash (Aug. 22, 2022)
  When Flash is external to the SoC, memory is no longer a limiting factor. Developers can select a best-in-class SoC based on its performance and scale Flash density independently. Being able to right-size Flash memory also reduces system cost and footprint.
  
  
• Serial Peripheral Interface. SPI, these three letters denote everything you asked for (Aug. 18, 2022)
  This article focuses on the most important details of the modern SPI interfaces, which are improved by many useful features. But to start, let us discover the history of the modern SPI interface, because even the old, most basic SPI interfaces are still in use.
  
  
• MIPI in next generation of AI IoT devices at the edge (Aug. 08, 2022)
  One of the original benefits of processing in the cloud in was simply to expand beyond the limited capacity of on-site processing. With advancements in AI, more and more decisions can be made at the edge. It is now clear that edge and cloud processing are complementary technologies; they are both essential to achieve optimal system performance. Designers of connected systems must ask, what is the most efficient system partitioning between the cloud and edge?
  
  
• Getting started in structured assembly in complex SoC designs (Aug. 04, 2022)
  The integration level of a system-on-chip (SoC) is defined in RTL, just like the rest of the design. Historically, RTL has been built through text editors. However, a decade or more ago, the sheer complexity of that task for the largest SoCs became unmanageable; now, most SoCs cross that threshold. Why is this?
  
  
• A Generic Solution to GPIO verification (Aug. 01, 2022)
  This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.
  
  
• Scalability - A Looming Problem in Safety Analysis (Jul. 27, 2022)
  The boundless possibilities of automation in cars and other vehicles have captivated designers to the point that electronic content is now a stronger driver of differentiation than any other factor. It accounts for a substantial fraction of material cost in any of these vehicles.