D&R Industry Articles | Most Popular | SoC News Alerts |

IP / SOC Products Articles

• Rethinking System-on-chip design at 65 nanometers and below (May. 17, 2006)
  The structure, composition, scale, or focal point of a new/incremental system design incorporates the talents and gifts of the designer using either a top-down or bottom-up design style. Is a centralized or distributed approach to processing the best appr
  
  
• Use compression where it's never gone before: A/D and D/A converters (May. 12, 2006)
  Compression is the science of making data representations smaller, in order to decrease the data's bandwidth and storage requirements.
  
  
• Embedded NVM adds flexibility to power management designs (May. 10, 2006)
  While today's designers have numerous NVM options, the field narrows to those that can be embedded at low cost, and yet also exhibit high performance and application flexibility
  
  
• Low Power USB 2.0 PHY IP for High-Volume Consumer Applications (May. 04, 2006)
  The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB intellectual property (IP), this semiconductor IP is far from commodity silicon
  
  
• A low-cost solution for FPGA-based PCI Express implementation (May. 03, 2006)
  The combination of a low-cost FPGA and an external physical interface (PHY) chip is uniquely positioned to displace costly, high-risk solutions such as ASICs.
  
  
• Video content protection using secure embedded non-volatile memory for HDMI with HDCP (Apr. 28, 2006)
  The proliferation of digital video and audio content has created a big problem for the owners of this content. How do you protect your intellectual property from illegal transfer to non-authorized users of music, movies, and other valuable entertainment a
  
  
• Start your crypto engine--cryptographic acceleration in SoCs (Apr. 21, 2006)
  Cryptographic offload engines span such markets as DRM, VPN, Storage and MACsec. Implementing configurable engines enables you to meet performance requirements while preserving gate count economics required by end market cost goals of SoC designers. Here'
  
  
• Challenges in PCI Express IP Implementation (Apr. 20, 2006)
  IP selection, verification and integration are key aspects to the success of an IP-based design. This paper describes some of the challenges imposed by an IP based implementation of the technology and discusses about possible solutions to address them.
  
  
• Get the right mix when integrating Power Management Solutions into SoCs (Apr. 19, 2006)
  With today’s consumer and wireless products such as MP3 players and cell phones requiring smaller form-factors, a wider range of supply voltages, reduced component costs, and increased reliability, design engineers need to be able to integrate more analog
  
  
• A hierarchy of needs for SoC IP reuse (Apr. 18, 2006)
  The semiconductor intellectual property (IP) industry is about 15 years old, but it seems that we are still far away from the dream of effective IP reuse on the scale that we need. In the early days, companies could have a legitimate IP make versus buy di
  
  
• Send your 3D graphics content over OCP (Apr. 17, 2006)
  As more handsets incorporate 3D graphics functions, a standard interface such as OCP becomes critical
  
  
• Video processor basics for consumer applications (Apr. 13, 2006)
  In this article, we explore the operation and characteristics of video codecs. We explain basic video compression algorithms, including still-image compression, motion estimation, artifact reduction, and color conversion. We discuss the demands codecs mak
  
  
• SoC processor is set for the big picture (Apr. 10, 2006)
  Today's demanding consumer video applications often require the high performance of system-on-chip integration, yet SoC processing engines have created new challenges for system developers. SoCs have traditionally been based on closed architectures, givin
  
  
• Streaming multimedia codecs on embedded/programmable DSPs (Apr. 10, 2006)
  Audio/video compression algorithms, as found in embedded DSPs, are the key to providing the real-time performance needed for streaming. These algorithms are known as codecs for their ability to code and decode digital data.
  
  
• Design an all-digital modulator with an RF output (Apr. 10, 2006)
  A software-defined radio (SDR) terminal promotes programmable realizations of the physical layer functionalities. A lot of research work has been done in applying DSPs and FPGAs to implement the baseband functionalities of the physical layer.
  
  
• Using programmable processor array chips for algorithmic-intensive tasks (Apr. 05, 2006)
  It's possible to use software-programmable architectures to emulate the advantages and flexibility of hardware-oriented tradeoffs.
  
  
• Transaction Level Model of IEEE 1394 Serial Bus Link Layer Controller IP Core and its Use in the Software Driver Development (Apr. 03, 2006)
  The paper describes a transaction level model of IEEE STD 1394a-2000 [1] link layer controller IP core and its use in the development of a software stack supporting this controller.
  
  
• Designing with an embedded soft-core processor (Mar. 30, 2006)
  When designing an embedded solution, the designer will have product level requirements that mandate the processing of various inputs to yield predictable outputs.
  
  
• How to choose the right IP for success (Mar. 27, 2006)
  Reusing internally developed intellectual property and incorporating third-party IP has become increasingly common in today's development teams as market pressures shorten market windows and Moore's Law continues to hold sway.
  
  
• FAUST: On-Chip Distributed SoC Architecture for a 4G Baseband Modem Chipset (Mar. 23, 2006)
  We describe our SoC implementation of a baseband subsystem for a high performance 4G terminal. Our architecture, called FAUST, is based on distributed synchronization and asynchronous communication. We highlight how we have actually implemented these two
  
  
• Designing A Real-Time HDTV 1080p Baseline H.264/AVC Encoder Core (Mar. 20, 2006)
  This paper describes an efficient implementation of a baseline H.264/AVC encoder core capable of encoding a 1920x1080 video stream in real time at 30 frames per second (HDTV 1080p).
  
  
• A technical overview of the CE-ATA storage interface (Mar. 20, 2006)
  Digital content is driving our society forward. Everywhere you turn there’s a new device with greater capacity ready to consume even more precious storage space. The digital content explosion is rapidly consuming available hard-disk drive (HDD) space and
  
  
• How to Create Efficient IP Standards and Why You Should Care (Mar. 13, 2006)
  Standards are designed to make communication between design blocks more effective and reduce the chance for errors, which can lead to poor design quality. Should we still care about standards when working with IP? Can an efficient standard be created? Wh
  
  
• Extending the SoC Architecture of 3G terminal to Multimedia Applications (Mar. 06, 2006)
  In this paper, a typical research case will be described on how to extend an existing SoC architecture of baseband processor on 3G terminal to the player on network multimedia compressed with MPEG-4, especially on how to build an effectively multi-layer a
  
  
• System synchronization styles and trends (Mar. 06, 2006)
  This article describes emerging trends in synchronizing digital ICs and shows how process scaling, rapid increases in clock frequencies, and demand for lower power dissipation will affect the choice of synchronization styles going forward.
  
  
• Using vector processing for HD video scaling, de-interlacing, and image customization (Mar. 03, 2006)
  Image processing is a challenging discipline: high processing power is required to calculate image adjustments in real-time. Since the standards by which a qualitative picture is measured by are relative, experts have to face a serious debate, as defining
  
  
• The state-of-play in multi-processor and reconfigurable computing (Feb. 21, 2006)
  When a conventional processor (core) cannot meet the needs of a target application, it becomes necessary to evaluate alternative solutions such as multiple cores and/or configurable cores.
  
  
• How to design a better 1.5-V 2.4-GHz CMOS PLL for wireless applications (Feb. 21, 2006)
  Since the VCO is one of the most important elements in the PLL system it is an appropriate place to begin this article, which addresses the challenges of designing a 1.5-V 2.4-GHz CMOS Phase Locked Loop (PLL) for wireless LAN applications. The design assu
  
  
• OTP firmware enhances processor flexibility (Feb. 20, 2006)
  Processor firmware must be upgradable to account for new algorithms or to simplify the development of derivative products. Storing such firmware in ROM or flash memory poses problems for embedded applications
  
  
• Enabling Rapid Adoption of the AMBA 3 AXI Protocol-based Design with Synopsys DesignWare IP (Feb. 16, 2006)
  The DesignWare® IP solution for the AMBA 3 AXI protocol enables designers to quickly and easily integrate the high-speed protocol into their (SoC) designs, while reducing risk and speeding time to results