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IP / SOC Products Articles

• High Speed Connected Component Labeling as a Killer Application for Image Recognition Systems by Dynamically Reconfigurable Processor (Feb. 16, 2006)
  This paper explains DAPDNA-2 architecture followed by the new CCL algorithm, DAPDNA-2 implementation, development tool, and experimental results. Finally an application example of the labeling engine IP is introduced followed by the conclusion
  
  
• Reengineering the obsolete semiconductor (Feb. 13, 2006)
  The question is, what are the key considerations when looking for a partner to produce obsolete parts for your mission-critical application? These basic due-diligence Do's and Don'ts can help you to make the right moves.
  
  
• CE-ATA: Consumer Electronics Storage Technology Introduction and Hardware Design Challenges (Feb. 09, 2006)
  This paper introduces an overview of the state-of-the-art technology underneath the hood of the CE-ATA industry’s storage standard. The paper addresses an explanation of the standard which leverages existing and proven technologies such as ATA and MMC (Mu
  
  
• Debug IP for SoC Debug (Feb. 02, 2006)
  This paper shows, by example, typical problems encountered by embedded systems programmers and how the new ARM® CoreSight™ technology can be deployed to give the developer the maximum visibility in to the chip’s operations and malfunctions
  
  
• Choosing hardware IP (Feb. 01, 2006)
  As with any complex technology, embedded systems developers have many factors to consider when selecting a design partner in today's semiconductor market, particularly if planning to convert FPGAs to ASICs.
  
  
• Building a Total Quality Experience into Silicon IP - Delivering DesignWare Silicon IP into SoC Designs (Jan. 26, 2006)
  It's time for a new supplier-buyer relationship - SIP vendors must deliver a Total Quality Experience to SIP buyers
  
  
• Market-Driven Open-Cores SoC-Experience (Jan. 23, 2006)
  The SoC content is defined by market needs and changes every half a year. The SoC methodology is driven by silicon technology and changes every 16 months
  
  
• On-chip di/dt Detector IP for Power Supply (Jan. 09, 2006)
  This paper demonstrates an on-chip di/dt detector IP. The di/dt detector core consists of a power supply line, an underlying spiral inductor and an amplifier
  
  
• A NoC-Based Communication Framework for Seamless IP Integration in Complex Systems (Jan. 03, 2006)
  In this paper, we present a NoC-based communication framework that is used to develop complex chips including a large number of heterogeneous IPs
  
  
• A Flexible, Low Power, High Performance DSP IP Core for Programmable Systems-on-Chip (Dec. 19, 2005)
  In this paper, the MontiumTM DSP core is introduced and an example is given of how this core can be used in programmable systems-on-chip.
  
  
• Successful Use of an Open Source Processor in a Commercial ASIC (Dec. 15, 2005)
  Here we describe our experience in using the LEON processor in a commercial ASIC. Both benefits and drawbacks are described before concluding that LEON was an excellent solution for this design
  
  
• An analysis of FPGA-based UDP/IP stack parallelism for embedded Ethernet connectivity (Nov. 28, 2005)
  We present three different UDP/IP stack cores, with different grades of parallelism and suited for various network demands. We show that the UDP/IP core area can be reduced to 1/3 of the original size with an appropriate implementation, accomplished by a
  
  
• Methodology for advanced flip-chip ASICs (Nov. 21, 2005)
  This article focuses on organic buildup routing, the predominant methodology for large flip-chip ASIC packages. It's important to note that most signal routing occurs in the upper layers of a buildup substrate, because the core vias' large size inhibits r
  
  
• Cluster-based approach eases clock tree synthesis (Nov. 14, 2005)
  This article discusses strategies for skew management in DSM designs. It covers the role of skew in a design, the types of clock trees used in current technology, the effective use of customized cluster based clock-tree synthesis (CTS), the merits of clus
  
  
• ZigBee SoCs provide cost-effective solutions (Nov. 08, 2005)
  In a near future, our homes and workplaces will have wireless networks that control and monitor daily tasks autonomously or on command enhancing our comfort and safety. Several of these networks will be based on the ZigBee wireless technology and the unde
  
  
• Bringing ARM7(TM) to the Masses (Oct. 27, 2005)
  Combining the flexibility of Actel Flash-based ProASIC3 devices with the industry-standard ARM7 creates a complete and powerful product that is easy to use
  
  
• Blistering traffic speeds: a detailed look inside PCI Express (Oct. 24, 2005)
  PCI Express is a scalable bus that provides as little as 250Mbytes/second at a 2.5Ghz signaling rate up to 8Gbytes/second in the first spec revision. Higher bandwidths can be achieved by increasing clock speed or bus width
  
  
• How to cut power consumption for high-speed apps with A/D converter architecture (Oct. 19, 2005)
  By Mark Holdaway, Director of Product Marketing A/D converter Products, Xignal
  
  
• Designing ASICs for supersystems (Oct. 14, 2005)
  During the past five years, ASIC system-on-chip design has taken on a new dimension — namely, that of ASIC SSOC (supersystem-on-chip) design
  
  
• Building an efficient ecosystem (Oct. 14, 2005)
  This article will describe the IP ecosystem and discuss some aspects with respect to hard IP (mixed signal, RF, digital, for example). It will outline some of the challenges companies face today and methods being taken to advance this topic
  
  
• Achieving Compliance and Interoperability for Your PCI Express Design (Oct. 13, 2005)
  This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
  
  
• FPGA Soft Processor Design Considerations (Oct. 12, 2005)
  FPGA technology and soft processor cores have the potential to integrate system design into a single FPGA device. From definitions to implementation, what do you need to know to get there?
  
  
• Architecture and Implementation of the ARM Cortex-A8 Microprocessor (Oct. 10, 2005)
  The Cortex-A8 processor spans a range of performance points depending on the implementation, delivering over to 2000 Dhrystone MIPS (DMIPS) of performance for demanding consumer applications and consuming less than 300mW for low-power mobile devices
  
  
• Static and dynamic modeling for high-density memories (Oct. 10, 2005)
  As designs increase in complexity, the density of memories that they connect to has also increased. It is not uncommon to see gigabyte memories. Having large memories comes with its own set of challenges during the verification stage.
  
  
• Video current D/A converters: some fundamentals for IP use (Oct. 06, 2005)
  by John Kusching, vice president of engineering, Qualcore Logic, Inc.
  
  
• Tips for maximizing RapidIO (Oct. 03, 2005)
  RapidIO is an open, standards-based interconnection technology for midsize and large embedded systems. It enables packet-switched, peer-to-peer connections among ASICs, DSPs, FPGAs, microprocessors, network processors and backplanes, with speeds of up to
  
  
• Simplifying DSP Hardware Development within a MATLAB-based Design Flow (Sep. 22, 2005)
  by Eric Cigan, AccelChip Inc. & Ir. Aaik van der Poel, Synopsys
  
  
• TD-SCDMA serves as a new battleground for 3G (Sep. 20, 2005)
  by Zoran Zvonar, Analog Devices
  
  
• Multiprocessor design for SoCs (Sep. 19, 2005)
  Multiple-processor design changes the role of processors, making it possible to design programmability into many functions while keeping power budgets under control
  
  
• Using FPGAs to Improve the Performance of Radar, Navigation and Guidance Systems (Sep. 15, 2005)
  By AccelChip