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IP / SOC Products Articles

• Unleashing the Power of Embedded DRAM (Mar. 01, 2005)
  Unleashing the Power of Embedded DRAM
  
  
• Vertical Solution for PCI Express (Feb. 25, 2005)
  Vertical Solution for PCI Express
  
  
• Philips Semiconductors Next Generation Architectural IP ReUse Developments for SoC Integration (Feb. 25, 2005)
  Philips Semiconductors Next Generation Architectural IP ReUse Developments for SoC Integration
  
  
• Reducing Time To Market for System On Chip Using IP Development and Integration Flow (Feb. 22, 2005)
  Reducing Time To Market for System On Chip Using IP Development and Integration Flow
  
  
• Die-level process monitor for mixed signal designs (Feb. 11, 2005)
  Die-level process monitor for mixed signal designs
  
  
• Test and Design Reuse (Feb. 11, 2005)
  Test and Design Reuse
  
  
• SoCs Let Designers Re-Architect Next-Gen Transport Equipment (Feb. 08, 2005)
  SoCs Let Designers Re-Architect Next-Gen Transport Equipment
  
  
• NetComposer-II: High performance Structured ASIC Programmable NPU platform for layer 4-7 applications (Feb. 04, 2005)
  NetComposer-II: High performance Structured ASIC Programmable NPU platform for layer 4-7 applications
  
  
• Competitive Advantages of the Mali Graphics Architecture (Feb. 01, 2005)
  Competitive Advantages of the Mali Graphics Architecture
  
  
• How memory architectures affect system performance (Jan. 31, 2005)
  How memory architectures affect system performance
  
  
• Accelerating Fixed-Point Design for MB-OFDM UWB Systems (Jan. 26, 2005)
  Accelerating Fixed-Point Design for MB-OFDM UWB Systems
  
  
• An IP core based approach to the on-chip management of heterogeneous SoCs (Jan. 25, 2005)
  An IP core based approach to the on-chip management of heterogeneous SoCs
  
  
• High-Speed Serial fully digital interface between WLAN RF and BB chips (Jan. 14, 2005)
  High-Speed Serial fully digital interface between WLAN RF and BB chips
  
  
• FPGA-Based DPLL Approach Delivers Wide-Lock Range (Jan. 11, 2005)
  While analog phase-lock loops (PLLs) still have a home in communication equipment, there is a clear shift in the sector toward implementing digital PLLs (DPLLs) in comm ASIC designs. For example, in some communication systems, designers need to implement a synchronous serial port without a separate line to an external clock. To make this happen, designers need to implement a DPLL that delivers wide input jitter and wide frequency ranges.
  
  
• Array Processors Enable Flexibility in FFT Designs (Dec. 29, 2004)
  Array Processors Enable Flexibility in FFT Designs
  
  
• Bridging a gap with peripherals (Dec. 17, 2004)
  Bridging a gap with peripherals
  
  
• SoC package design takes 'bottom-up' tack (Dec. 16, 2004)
  SoC package design takes 'bottom-up' tack
  
  
• SiPs offer alternative to SoCs for comms (Dec. 16, 2004)
  SiPs offer alternative to SoCs for comms
  
  
• Bringing Order to Multi-Core Processor Chaos (Dec. 09, 2004)
  Improvements in silicon process technology — 130 to 90 to 65 nm — have brought system-on-chip (SoC) devices with multiple embedded processors to mainstream applications ranging from consumer-level handsets sporting multimedia functionality to high-density network infrastructure equipment. Multi-core approaches keep hardware design in the low frequency domains (e.g. less power and heat), offering significant price, performance, and flexibility over higher speed single-core designs.
  
  
• Platform MCUs Give Maximum Return (Dec. 03, 2004)
  Platform MCUs Give Maximum Return
  
  
• Migration path laid to low-cost 32-bit MCUs (Dec. 03, 2004)
  Migration path laid to low-cost 32-bit MCUs
  
  
• The why, where and what of low-power SoC design (Dec. 02, 2004)
  The why, where and what of low-power SoC design
  
  
• 8-bit microcontrollers: still going . . . (Dec. 02, 2004)
  8-bit microcontrollers: still going . . .
  
  
• Semiconductor options for real-time signal processing (Nov. 25, 2004)
  Semiconductor options for real-time signal processing
  
  
• 'Wrap' your cores to enable SoC test (ARM & Synopsys) (Nov. 24, 2004)
  'Wrap' your cores to enable SoC test (ARM & Synopsys)
  
  
• Use macrocells to automate analog/mixed-signal design (Nov. 19, 2004)
  Use macrocells to automate analog/mixed-signal design
  
  
• Power Islands: The Evolving Topology of SoC Power Management (Nov. 16, 2004)
  Power Islands: The Evolving Topology of SoC Power Management
  
  
• How platform-based design cuts digital still camera design time and costs (Nov. 15, 2004)
  How platform-based design cuts digital still camera design time and costs
  
  
• Digital Power Control Highlights (Nov. 09, 2004)
  Digital Power Control Highlights
  
  
• No size fits all for signal processing on FPGA (RF Engines) (Nov. 02, 2004)
  No size fits all for signal processing on FPGA (RF Engines)