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IP / SOC Products Articles
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Navigating the Reef: Supplying IP That Works For You and Your Customer (Nov. 04, 2004)
Navigating the Reef: Supplying IP That Works For You and Your Customer
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Relational physical design: no absolutes (ReShape) (Nov. 02, 2004)
Relational physical design: no absolutes (ReShape)
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Reality check for configurable IP blocks (IPextreme) (Nov. 02, 2004)
Reality check for configurable IP blocks (IPextreme)
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Verification issues for reconfigurable IP (Actel) (Nov. 02, 2004)
Verification issues for reconfigurable IP (Actel)
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Reuse of Analog Mixed Signal IP for SoC Design: Progress Report (Cadence Design Systems) (Nov. 01, 2004)
Reuse of Analog Mixed Signal IP for SoC Design: Progress Report (Cadence Design Systems)
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Achieving Reuse with both Modifiable IP and Configurable IP (LSI Logic) (Nov. 01, 2004)
Achieving Reuse with both Modifiable IP and Configurable IP (LSI Logic)
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System view of core clock frequency, voltage (Oct. 28, 2004)
System view of core clock frequency, voltage
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The fixed processor is dead, long live the battery (Oct. 28, 2004)
The fixed processor is dead, long live the battery
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Low Power System Design Techniques Using FPGAs (Oct. 28, 2004)
Low Power System Design Techniques Using FPGAs
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Semiconductor strategies for low power consumption (Oct. 25, 2004)
Semiconductor strategies for low power consumption
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'Cool IC' design vital for multi-gigabit system design (Oct. 25, 2004)
'Cool IC' design vital for multi-gigabit system design
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Wireless focus: more channels/mW (Oct. 25, 2004)
Wireless focus: more channels/mW
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Realising the Full Potential of Multi-core Designs (Oct. 22, 2004)
Realising the Full Potential of Multi-core Designs
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Digital RF techniques ease chip integration challenges (Oct. 15, 2004)
Digital RF techniques ease chip integration challenges
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Flexible Embedded Processors for Developing Multi-Standard OFDM Broadcast Receivers (Oct. 15, 2004)
Flexible Embedded Processors for Developing Multi-Standard OFDM Broadcast Receivers
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Unlock and Load: Characterizing Today's PLLs (Oct. 13, 2004)
The phase-locked loop (PLL) has become one of the most versatile tools in the communication sector. PLLs are at the heart of circuits and devices ranging from clock recovery blocks in data communications systems to the local-oscillators that power cellular phones. And since their output frequency is always an exact multiple of the reference frequency, PLLs are the circuit of choice for frequency synthesizers, synchronous systems that require clock alignment and myriad applications, such as tracking satellite Doppler shift and sensing minute reactance changes in industrial proximity sensors.
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New DSP Technology for Multimode Wireless (Oct. 12, 2004)
New DSP Technology for Multimode Wireless
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Single-chip radio raises design questions (Oct. 12, 2004)
Single-chip radio raises design questions
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Enabling multimode handsets (Oct. 12, 2004)
Enabling multimode handsets
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Software-defined radio is not yet on call (Oct. 12, 2004)
Software-defined radio is not yet on call
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Integration key to multimode era (Oct. 12, 2004)
Integration key to multimode era
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Architecture options for convergent devices (Oct. 12, 2004)
Architecture options for convergent devices
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Selecting PLLs for ASIC Applications Requires Tradeoffs (Oct. 12, 2004)
Selecting PLLs for ASIC Applications Requires Tradeoffs
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RF integration: Changing the face of test (Oct. 08, 2004)
RF integration: Changing the face of test
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Process Improvements for System on Chip developments (Oct. 08, 2004)
Process Improvements for System on Chip developments
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Restoring predictability in SoC integration (Oct. 08, 2004)
Restoring predictability in SoC integration
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IP reuse simplifies SoC design, verification (Oct. 08, 2004)
IP reuse simplifies SoC design, verification
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Designing an optimal wireless SoC (Oct. 08, 2004)
Designing an optimal wireless SoC
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IP Cores for FPGAs (Oct. 08, 2004)
IP Cores for FPGAs
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FPGA's vs. ASIC's (Sep. 09, 2004)
FPGA's vs. ASIC's