Dolphin Integration Announces Memory Compiler Haumea at 65 nm

March 27, 2009 -- The HAUMEA memory line serves the major need for SoC Integration with the best compromise between Low power Consumption and Density.

Haumea additionally offers new flexibilities to both reduce the number of mask layers and simplify interconnections celebrated as the “SIMPLER” layout implementation, for Simple Interconnections of Memory for PLacE and Router. New benchmarks for the P&R specialists are available on request.

This generation of Haumea addresses the 65 nm LP process with compilers for both RAM and ROM.

The third generation Haumea compiler enables full optimization, without interpolations, actually granting the best density and ultra Low power Consumption of each instance.

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About Dolphin

Dolphin Integration is up to their charter as the most adaptive creator in Microelectronics to "enable mixed signal Systems-on-Chip", with a quality management stimulating reactivity for innovation.
Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.