Altera Enables Customer Design Starts for 14 nm Stratix 10 FPGAs and SoCs

San Jose, Calif., August 4, 2014 – Building on the success of early customer benchmarking results announced earlier this year, Altera Corporation (Nasdaq: ALTR) today released early access design software for Stratix® 10 FPGAs and SoCs, the industry’s first design software targeting 14-nm FPGAs. Customers today can start their Stratix 10 designs and experience firsthand the 2X core performance gains they can achieve as a result of the Stratix 10 HyperFlex™ architecture and the Intel 14 nm Tri-Gate process. With this design software, Altera introduces the Hyper-Aware design flow which includes the innovative Fast Forward Compilation capability that allows customers to perform rapid design performance exploration and attain breakthrough levels of performance.

With the breakthrough leap in core performance that Stratix 10 FPGAs deliver, users are now able to unlock the performance in their designs by taking advantage of the innovative capabilities of the HyperFlex architecture to reach breakthrough levels of performance not possible in previous generation FPGA architectures. Developed to enable 2X performance in a customer’s design, Fast Forward Compilation pinpoints performance bottlenecks and provides detailed, step-by-step performance improvement recommendations that a user can rapidly implement. Users also receive Fmax (maximum operating frequency) estimates of their design that can be achieved by applying the recommendations Fast Forward Compilation provides. With this innovative design flow, Fast Forward Compilation gives customers an opportunity to maximize overall design performance made possible by Stratix 10 FPGAs and SoCs and achieve rapid timing closure.

“The Stratix 10 design tools we offer today provide customers the fastest path to market for the industry’s highest performance, next-generation FPGAs and SoCs,” said Jordon Inkeles, senior marketing manager, high-end FPGAs, at Altera. “Fast Forward Compilation with the Stratix 10 HyperFlex architecture enables customers to double their performance while simultaneously shaving off weeks to months of engineering development time.”

Previously, in order to achieve high-performance targets, users often needed to undergo multiple, time-consuming design iterations, including trying various design optimizations and re-running full FPGA compiles to determine the effectiveness of design changes. With Fast Forward Compilation, users receive detailed guidance for design optimization and an estimated design Fmax to leverage the HyperFlex architecture. With these insights, customers are better able to make decisions for where to most effectively invest development time to increase their design’s performance and throughput, taking the guesswork out of performance exploration. As a result, Stratix 10 FPGA and SoC customers perform fewer design iteration cycles to achieve their performance targets and simplify the path to achieving 2X core performance gains.

About Stratix 10 FPGAs and SoCs
Stratix 10 FPGAs and SoCs are designed to enable the most advanced, highest performance applications in the communications, military, broadcast and compute and storage markets, while slashing system power. Stratix 10 FPGAs and SoCs deliver on average a 2X core performance increase over previous generation high-performance programmable devices as a result of the HyperFlex architecture and the Intel 14 nm Tri-Gate process. HyperFlex – Altera’s next-generation core fabric architecture for Stratix 10 devices – represents the FPGA industry’s most significant leap in architectural innovations in over a decade and enables applications not possible using conventional FPGA architectures. For high-performance systems that have strict power budgets, Stratix 10 devices allow customers to achieve up to a 70 percent reduction in power consumption compared with Stratix V FPGAs. Stratix 10 FPGAs and SoCs also provide the industry’s highest levels of system integration, which include:

• The highest density monolithic device with greater than four million logic elements.
• Over 10 TeraFLOPs of single-precision, hardened floating point DSP performance.
• More than 4X serial transceiver bandwidth compared to previous generation FPGAs, including 28-Gbps backplane capable transceivers and a path to 56-Gbps transceivers.
• A high-performance, quad-core 64-bit ARM Cortex-A53 processor system.
• Multi-die solutions capable of integrating DRAM, SRAM, ASIC, processors and analog components in a single package.

Availability
Stratix 10 design software is available today for customers enrolled in Altera’s Stratix 10 early access program. Customers within the early access program can contact their local Altera sales representative to request a software license. For additional information regarding Stratix 10 FPGAs and SoCs, or to join the early access program, visit the software innovations page on Altera’s web site.

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