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Commentary / Analysis

• Networking concepts inspire next-gen SoCs (Monday Jul. 18, 2005)
  Your office computer network may be a model for next-generation IC designs, said system-on-chip experts who gathered in this small village in the French wine country last week
  
  
• Leaky chips test designers' Skills (Monday Jul. 18, 2005)
  The growing popularity of battery-powered portable products and their demanding feature sets require designers to eat and sleep power consumption. That means considering new approaches, such as turning off parts of a chip that aren't mission-critical or d
  
  
• SoC programming models needed, researchers say (Thursday Jul. 14, 2005)
  Programming models must improve to make full use of next-generation systems-on-chip (SoCs), according to presenters at the Multi-Processor SoC (MPSoC) workshop here Thursday
  
  
• Researcher calls for 'software-centric' SoC design (Tuesday Jul. 12, 2005)
  The problem with system-on-chip (SoC) design is that software and hardware designers live in separate worlds, according to Hiroaki Takada, professor of information at Nagoya University in Japan and developer of a 'software-centric' system-level design sys
  
  
• Innovation drives SoC performance, keynoters say (Monday Jul. 11, 2005)
  While CMOS scaling will continue to reduce costs, system-on-chip (SoC) performance improvements will depend on innovations that produce integrated design systems, said IBM's Lisa Su at a keynote speech at the Multiprocessor SoC (MPSoC) forum here Monday (
  
  
• The RISC that did not pay off (Monday Jul. 11, 2005)
  John Bourgoin, chairman and CEO of MIPS Technologies, keynoted an analyst event recently. He outlined the history of RISC architectures in silicon and cited some problems that CPU designers face
  
  
• Making the switch from NOR to NAND flash (Monday Jul. 11, 2005)
  The shift from NOR to NAND flash is not always smooth. Though cost-effective and much higher in performance, NAND is considered unreliable and complicated to manage
  
  
• Structured ASICs deserve serious attention at 90 nm (Thursday Jul. 07, 2005)
  Four years after ASIC vendors introduced their first structured-ASIC devices in response to FPGA vendors eating up their market share, the structured-ASIC market has yet to become a popular choice for logic designs
  
  
• Customers using ASICs move to 32-bit MCUs (Thursday Jul. 07, 2005)
  Many customers that have primarily used ASIC design in the past have recently begun to move toward using and evaluating microcontroller (MCU)-based systems
  
  
• The to and fro of DSP/RISC Convergence (Monday Jul. 04, 2005)
  In today's connected-computing environment, many of the hottest application areas can be found in consumer, home and industrial electronics, where the capabilities of both interrupt-driven RISC controllers and flow-oriented digital signal-processing engin
  
  
• ARCHITECTURES: USB 2.0 climbs aboard silicon (Monday Jul. 04, 2005)
  Initial problems with USB intellectual property for systems-on-chip (SoCs) have led some systems designers to ask if there isn't an intermediate level that still integrates the USB device into something, but doesn't entail all the risk of putting it on th
  
  
• ARCHITECTURES: Printers crank out new SoC requirements (Monday Jul. 04, 2005)
  As the IC industry comes increasingly to depend on consumer markets for its living, it is learning that small shifts in consumer habits can pose huge technical problems for chip designs. One such shift is confronting makers of controller systems-on-chip f
  
  
• An IP storm? (Thursday Jun. 23, 2005)
  The continuously increasing number of components that silicon vendors are fitting onto a single chip has been driving the need for a correlating increase in developer productivity
  
  
• Philips Semiconductors CEO sets out platform for the future (Thursday Jun. 23, 2005)
  Philips Semiconductors CEO sets out platform for the future
  
  
• The search for semiconductor IP intensifies (Monday Jun. 20, 2005)
  Simple arithmetic can show the necessity for intellectual-property reuse in system-level chip design. A modest system-on-chip requires millions of gates. Each designer is capable of averaging perhaps a few tens of fully verified gates per day. Unless subs
  
  
• Platform ASICs a natural fit at 90 nm, say DAC panelists (Friday Jun. 17, 2005)
  Panelists debating the merits of platform ASICs agreed designers are entering an era of more uncertainty at the 90-nm process node than at any other technology shift.
  
  
• IP is an Ecosystem, Denali Says (Thursday Jun. 16, 2005)
  
  
  
• IP verification panel advocates standards (Wednesday Jun. 15, 2005)
  Intellectual property (IP) verification poses a tremendous challenge and the industry should move to create and adopt standards for interoperability and compliancy, according to a panel of verification experts held here Wednesday at the Design Automation
  
  
• Panelists Discuss IP-vendor Survival Strategies (Wednesday Jun. 15, 2005)
  Panelists Discuss IP-vendor Survival Strategies
  
  
• IP gurus discuss interoperability (Tuesday Jun. 14, 2005)
  Industry executives debated IP interoperability at the Design Automation Conference
  
  
• Analog, mixed-signal set to invigorate IP market, says Gartner (Monday Jun. 13, 2005)
  The intellectual property (IP) market — as it refers to predefined circuit blocks — is far from dead and is becoming more diverse through the rise of vendors of analog and mixed-signal IP, according to Christian Heidarson, an analyst with Gartner Inc., sp
  
  
• Gartner Dataquest analyst gives ASIC, FPGA markets clean bill of health (Monday Jun. 13, 2005)
  The application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) markets are in good health, according to Bryan Lewis, vice president and chief semiconductor analyst for Gartner Dataquest
  
  
• Trading analog intellectual property (Monday Jun. 13, 2005)
  When I looked into possible ways to solve some of the problems that block the trade of analog intellectual property recently, some interesting ideas emerged
  
  
• Power issues heat up chip forum (Friday Jun. 10, 2005)
  A difference of opinion about power management strategy generated some heat, if not sparks, at the Semico Impact Conference on Intellectual Property here
  
  
• Interview - Gary Meyers, president and CEO of Synplicity : FPGA or ASIC? (Monday Jun. 06, 2005)
  Gary Meyers, president and CEO of FPGA tool vendor Synplicity, sat down with Electronic News to talk about what’s changing in the EDA industry. What follows are excerpts of that conversation.
  
  
• Doors 'open' to hardware (Monday Jun. 06, 2005)
  Is 'open' hardware a disruptive technology that will foster the kind of collaboration that Linux brought to the software world?
  
  
• Toshiba: No money in structured Asics (Thursday Jun. 02, 2005)
  Structured Asics are not making any money, according to Toshiba, while full-scale SoCs are costing a lot less than people think
  
  
• The design-service challenge: Q&A with Global Unichip (Wednesday Jun. 01, 2005)
  The global semiconductor industry is now seeing close cooperation between outsourced design and foundry
  
  
• In Corrigan's wake, whither LSI Logic? (Monday May. 30, 2005)
  As Wilfred J. Corrigan handed over the titles of president and chief executive officer of LSI Logic Corp. to his reportedly hand-picked successor, Intel's Abhi Talwalkar, last week, industry watchers were assessing Corrigan's legacy even as they pondered
  
  
• Is day of the architect over? (Monday May. 23, 2005)
  What's to become of the generation of designers who grew up aspiring to be computer architects? With even Intel throwing in the towel on making faster CPU cores and switching its focus to on-chip multiprocessing, it appears that the age of the architect i