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IP / SOC Products News

• eSilicon and MIPS Technologies Announce Tapeout of 28nm 1.5GHz Microprocessor Cluster for Embedded Platforms (Wednesday Oct. 05, 2011)
  eSilicon and MIPS Technologies announced the tapeout of a high-performance, three-way microprocessor cluster on GLOBALFOUNDRIES' leading-edge, low-power 28nm-SLP process technology.
  
  
• Alvand Technologies Offers Analog Mixed-Signal IP in 28nm Process (Wednesday Oct. 05, 2011)
  Alvand Technologies today announced that it will be offering Analog Front End (AFE) IP for wireless (MIMO) applications in GLOBALFOUNDRIES' 28nm foundry process.
  
  
• MoSys Demonstrates Bandwidth Engine IC Interoperability with Avago Technologies SerDes (Tuesday Oct. 04, 2011)
  MoSys' Bandwidth Engine SerDes is compatible with the OIF CEI-11 specification allowing it to interface with high-performance network processing ASICs such as those available from Avago Technologies.
  
  
• Memoir Systems Introduces Groundbreaking Technology for Networking and Multicore SoC Products (Monday Oct. 03, 2011)
  Memoir Systems(R) Inc., a Semiconductor Intellectual Property (SIP) venture-backed start-up with technology that delivers breakthrough embedded memory performance, today announced its initial targeted products. The company's patent-pending Algorithmic Memory(TM) technology provides an order of magnitude increase in embedded memory performance. Memoir's technology can also lower embedded memory area and power consumption, shorten memory development time, and provide versatility benefits.
  
  
• Analog Bits Expands SERDES Product Line to Include SONET Grade IP (Monday Oct. 03, 2011)
  Analog Bits has added a SONET Grade Programmable Low Power IP to its expanding SERDES product line.
  
  
• Silicon Infusion Announces 3-Layer ISDB-T Demodulator (Monday Oct. 03, 2011)
  The Zaltys 3-Layer ISDB-T High Performance Demodulator (ISDBT-D) core is now available from Silicon Infusion. It integrates a high performance COFDM demodulation engine, and a fully compliant deframer, to give a complete and flexible ISDB-T demodulation solution.
  
  
• RivieraWaves announces the world's first qualified baseband IP for dual mode Bluetooth 4.0 (Monday Oct. 03, 2011)
  RivieraWaves announced today that it has successfully passed the Bluetooth Qualification with its dual mode Bluetooth 4.0 baseband Intellectual Property (IP).
  
  
• Arasan Chip Systems Announces ONFI 3.0 NV-DDR2 PHY and Patent Pending Dynamically Configurable ECC technology for NAND Flash Controller (Friday Sep. 30, 2011)
  Arasan announced today that the company added an ONFI 3.0 PHY to its Flash Storage solution. Arasan’s existing ONFI 3.0 NAND Flash Controller with patent pending dynamically configurable ECC technology seamlessly integrates with the new PHY to form an easy to use, high-performance Flash Storage solution
  
  
• Xylon Announces New SD Host Controller IP for Xilinx FPGAs (Friday Sep. 30, 2011)
  Xylon's logiSDHC SD Host Controller IP core now supports Xilinx® 7 Series FPGAs and the ARM® AMBA® AXI4 bus. The new version of Xylon's Secure Digital Host Controller for SD memory and MMC cards enables users to easily add mass storage capabilities to their Xilinx FPGA design.
  
  
• HDL Design House announces new MIPI IP products (Tuesday Sep. 27, 2011)
  With more than five years of industry experience in developing MIPI standards for different SoC in mobile applications, HDL Design House MIPI expert team currently has more than 25 specialists with expertise in different MIPI protocols that enable us to provide our customers with fast and efficient deployment of the new MIPI based products.
  
  
• Altera Delivers Industry's First FPGA-based Serial RapidIO Gen2 Solution Enabling Next-Generation Wireless Base Station Deployments (Monday Sep. 26, 2011)
  Altera today announced the availability of the industry's first Serial RapidIO® Gen2 FPGA based solution, enabling improved bandwidth and link flexibility for next-generation 3G and 4G wireless base station deployments. Altera successfully interoperated its RapidIO MegaCore® Function IP core implemented in a Stratix® IV GX FPGA with a Serial RapidIO® Gen 2 switch from Integrated Device Technology (IDT).
  
  
• Arasan Chip Systems Introduces USB 2.0 HSIC PHY IP (Friday Sep. 23, 2011)
  Arasan announced today the availability of its USB 2.0 HSIC PHY IP. The USB 2.0 HSIC (High Speed Inter Chip) Standard is being rapidly adopted by the mobile industry as a means of connecting subsystems within smartphones and tablets.
  
  
• Altior Announces State-of-the-Art Compression-Decompression File System Accelerator for High Performance Primary and Secondary Data Storage Applications (Tuesday Sep. 20, 2011)
  Altior has announced the availability of its AltraFlex™ Compression-Decompression File System (CeDeFS) Accelerator solution, which uses the industry-standard GZIP/GUNZIP data compression/decompression protocols to increase disk space and boost disk capacity utilization, seamlessly and transparently.
  
  
• Sonics Unveils Industry's First GHz Network-on-Chip (Tuesday Sep. 20, 2011)
  Sonics today announced SonicsGN™ (SGN), the industry’s first GHz network-on-chip (NoC) for advanced, concurrent applications processing and system-level design. SGN allows SoC designers to deliver high-performance, simultaneous application processing for smart phones, mobile video and tablets.
  
  
• Cadence Announces DFI 3.0-compliant Design and Verification IP (Tuesday Sep. 20, 2011)
  Cadence today announced it is offering a comprehensive suite of solutions in support of the latest DDR PHY Interface (DFI) 3.0 specification (also announced today by the DFI Technical Group).
  
  
• Cosmic Circuits announces extensive 28nm roadmap (Friday Sep. 16, 2011)
  Cosmic Circuits has several IPs in various stages of development in 28nm technology. These include system-clocking PLLs, MIPI DPHY and MPHY, Wireless AFE and Monitoring ADCs.
  
  
• Dolphin Integration launches a 65 nm compiler for Dual Port Register Files reaching the highest density (Monday Sep. 12, 2011)
  The ERIS architecture for Dual Port Register File compiler, already available in 130 nm, is now adapted to the 65 nm and its shrunk version at 55 nm.
  
  
• Posedge Inc. Announces Its High Performance, Low Gate Count PE-SD3.01/SDIO3.0/eMMC4.5 Combo Device Controller IP (Monday Sep. 12, 2011)
  Posedge announces the availability of its upgraded PE-SD3.01/SDIO3.0/eMMC4.5 Combo Device Controller IP. The fully JEDEC compliant SD3.01/SDIO3.0/eMMC4.5 Combo Device Controller IP is highly configurable and completely compatible with all SD3.01/SDIO3.0 and eMMC4.5 protocols including ASSD2 (Advance Secure SD), eSD2.1 (Embedded SD) along with standard boot and alternate boot modes of operation.
  
  
• Sidense's NVM IP Completes TSMC IP9000 Assessment at 90nm Low-Power Process Node (Monday Sep. 12, 2011)
  Sidense adds SiPROM one-time programmable (OTP) memory macros at 90LP to growing list of products that meet TSMC’s IP9000 Assessment requirements.
  
  
• CEVA Announces Availability of Dolby Mobile Technology for CEVA-TeakLite-III DSP (Monday Sep. 12, 2011)
  CEVA's highly-optimized DSP implementation of third generation Dolby Mobile offers up to 5X power efficiency compared to CPU based approach
  
  
• Athena Announces Advanced True Random Number Generator (Monday Sep. 12, 2011)
  The Athena Group today announced the availability of the Advanced True Random Number Generator (TRNG), which meets the stringent requirements for random bit generators, both deterministic and non-deterministic, as specified in NIST SP800-90 and tracks FIPS 140-3 (draft).
  
  
• Xilinx Accelerates Broadcast Industry Adoption of Video Over IP at IBC 2011 (Thursday Sep. 08, 2011)
  Today Xilinx announced the availability of its SMPTE 2022-5/-6 intellectual property core, the company's newest building block for broadcast equipment developers delivering the internet protocol (IP) -based systems needed to cut the high cost of transporting raw, high-bit video from remote events, to studios, to post editing houses, and other points along the production process.
  
  
• Chipus provides IPs at SilTerra Technologies (Thursday Sep. 08, 2011)
  
  
  
• intoPIX enlarges its JPEG 2000 IP-core offering on Altera FPGA devices (Wednesday Sep. 07, 2011)
  intoPIX, the leading provider of JPEG 2000 IP-core solutions, today announced the availability of its products on the Altera® FPGA device families.
  
  
• RF Engines'HyperSpeed Plus offers unprecedented FPGA performance with 52 Giga Samples per Second Pipeline FFT cores (Wednesday Sep. 07, 2011)
  RF Engines Limited (RFEL) has set what it believes to be an unprecedented performance benchmark for commercially available Pipeline Fast Fourier Transform (PFFT) cores on FPGA
  
  
• Elliptic Technologies Debuts New Multi-Packet Processing Security Engine For High Capacity Wireless And Network Applications (Thursday Sep. 01, 2011)
  Elliptic Technologies unveiled today its latest security engine called the Multi-Packet Manager, a highly programmable and efficient security protocol accelerator with enhanced processing capabilities for multiple data streams.
  
  
• Kilopass Expands Embedded Non-Volatile Memory Offering To GLOBALFOUNDRIES' 0.13um G Process (Tuesday Aug. 30, 2011)
  Kilopass today announced that its XPM™ embedded one-time programmable (OTP) NVM technology has completed 1000 hours of JEDEC standard reliability testing for high temperature operating life (HTOL) and high temperature storage life (HTSL) on 3 lots for GLOBALFOUNDRIES’ 0.13um generic process technology.
  
  
• Cosmic Circuits tapes out MIPI MPHY in 85nm (Tuesday Aug. 30, 2011)
  Cosmic Circuits today announced the tape out of its MIPI MPHY solution in 85nm for use in eMMC devices.
  
  
• Silicon Image Expands IP Portfolio With High-Quality Video Processing Technology (Monday Aug. 22, 2011)
  Silicon Image today announced its new family of high-quality cineramIC™ video processing IP cores, ranging from scalers and deinterlacers to video enhancement solutions such as noise reduction and edge enhancement.
  
  
• Tensilica DSP core does 100 GMACs at 1W (Friday Aug. 19, 2011)
  Tensilica described a new DSP core for next-generation cellular applications that when made in a 28nm process can compute 100 GMACs/second at less than a Watt