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IP / SOC Products News

• Trilinear Technologies Adds DV Decode Solution to IP Core Portfolio (Monday Oct. 18, 2010)
  Trilinear Technologies today announced the newest member of its multimedia IP core family, the M11 DV Decoder. The M11 DV Decoder core is capable of decoding the full range of standard and high definition video resolutions including 480i, 576i, 720p and 1080i at both 50Hz and 60Hz.
  
  
• HDL Design House announces high performance serializer deserializer (SerDes) for Serial Rapid IO protocol 2.1 (HIPA 21000) IP core (Wednesday Oct. 13, 2010)
  HDL Design House has announced today the availability of the HIPA 21000, a high performance low cost serializer-deserializer (SerDes) meant to be used in the systems based on Serial RapidIO protocol.
  
  
• ARM and SMIC Extend Comprehensive Product Portfolio of Free Libraries of Physical IP to 65nm and 40nm LL Process Technology (Monday Oct. 11, 2010)
  ARM and SMIC today announced an agreement to collaborate on the development of ARM leading physical IP library platform for SMIC 65nmLL and 40nm LL technology process nodes. This agreement will provide free access on the ARM DesignStart™ online IP access portal to library suites of 9-track and 12-track multi-Vt logic libraries, power management kits, ECO kits and ARM high density optimized memory compilers.
  
  
• Evatronix Receives USB-IF Certification for Its SuperSpeed USB 3.0 Device IP Core (Monday Oct. 11, 2010)
  Evatronix SA, announces today its high performance SuperSpeed USB 3.0 Device Controller IP core has been officially certified by USB-Implementers ForumF, the organization behind the USB standards, as fully compatible with the latest version of the SuperSpeed USB 3.0 specification.
  
  
• MindTree Unveils IP Suite to Target Bluetooth Low Energy Market (Wednesday Oct. 06, 2010)
  MindTree announced the launch of BlueLitE, its single mode Bluetooth low energy (Bluetooth 4.0) Intellectual Property suite today. This IP offering complements MindTree's market proven classic Bluetooth (Bluetooth 2.1+EDR and 3.0) and Dual Mode Bluetooth low energy (4.0) suite of IPs. The BlueLitE IP suite will help the semiconductor manufacturers make a swift, smooth and effortless transition to tap the opportunities in the fast emerging Bluetooth low energy market.
  
  
• Qualcore Successfully validates USB 2.0 PHY in TSMC 90nm Technology (Wednesday Oct. 06, 2010)
  QualCore Logic today announced that it successfully validated USB 2.0 PHY for US based company - the leading providers of high performance non-volatile solid state drives.
  
  
• Xilinx ISE Design Suite 12.3 Introduces AMBA 4 AXI4 IP Cores, Enhances PlanAhead Design and Analysis Cockpit, Extends Power Optimization (Tuesday Oct. 05, 2010)
  Xilinx today announced the release of ISE(R) Design Suite 12.3, kicking-off the FPGA leader's roll-out of Intellectual Property (IP) cores that meet the AMBA(R) 4 AXI4(TM) specification for interconnecting functional blocks in System-on-Chip (SoC) design, as well as introducing productivity enhancements to the PlanAhead(TM) Design and Analysis cockpit, and Intelligent Clock Gating support for reducing dynamic power consumption in Spartan(R)-6 FPGA designs.
  
  
• OptNgn Delivers 2D-FFT FPGA Library Elements for use in Imaging and DSP applications (Friday Oct. 01, 2010)
  At processing rates of up to 306 complex mega pixels per second (Mpps), the new OptNgn 2DFFT FPGA library elements are the perfect choice for inexpensive, low power sensor data stream processing of convolution and filtering-based applications from video, medical, radar/sonar, and scientific-based real-time sources.
  
  
• Evatronix Enhances the JPEG2000 Video Encoder IP Core with HD Video Support and Increases Its Online Demo Bandwidth (Thursday Sep. 30, 2010)
  Evatronix SA, announced today its JPEG2000 Video Encoder IP core has been enhanced with two more configurable options and a set of architecture optimizations for yet better performance and fit into customer application. As of now, the JPEG 2000 Video Encoder features more than a dozen user configurable parameters and processes HD video at 30 frames per second.
  
  
• MIPS Technologies' New Processor Provides Fastest Fully-Synthesizable Multicore IP (Monday Sep. 27, 2010)
  MIPS Technologies today introduced a new processor that offers industry-leading speed for fully-synthesizable multicore IP. With the MIPS32® 1074K Coherent Processing System (CPS), companies can now get the high performance of a custom implementation with an off-the-shelf CPU core.
  
  
• Intilop corporation announces a record breaking lowest latency & highest bandwidth 10G bit TCP offload engine (Monday Sep. 27, 2010)
  Intilop today announced its flagship 10 G bit TCP Offload Engine that delivers highest throughput and least latency in the industry. The latency of ~100 ns was made possible by patent pending advanced dynamic array search architecture.
  
  
• Cortus and RivieraWaves Partner to Provide Complete Bluetooth Low Energy and Classic Bluetooth BR/EDR Low Power Platforms (Monday Sep. 27, 2010)
  Cortus and RivieraWaves announce a partnership providing a range of complete, turnkey, easy to integrate, Bluetooth IP solutions. One of the Platforms, coming out of this partnership, is a complete, fully qualified, Bluetooth Low Energy solution, specifically designed for ultra low power systems requiring exceptionally long battery life.
  
  
• Dolphin Integration: The first 16-bit MCU core 8051 upward compatible, achieving 0.4 DMIPS/MHz (Friday Sep. 24, 2010)
  The Enabler of mixed signal Systems-on-Chip unveils Flip80251-Hurricane, the latest member of its 16-bit microcontroller family; upward compatible with the i80251 legacy for best density, Flip80251-Hurricane offers increased addressing and processing power with the lowest power consumption.
  
  
• Open-Silicon, MIPS Technologies, and Dolphin Technology Achieve ASIC CPU Performance of Over 2.4GHz in TSMC 40nm (Tuesday Sep. 21, 2010)
  Open-Silicon, Inc., MIPS Technologies, Inc., and Dolphin Technology today announced the successful tapeout of a high-performance ASIC processor at over 2.4GHz under typical conditions.
  
  
• Lattice Announces Low Cost Programmable SPI-4.2 Solution (Monday Sep. 20, 2010)
  Lattice today announced the availability of its full rate SPI-4.2 solution based on a low cost, low power FPGA fabric. Consisting of a LatticeECP3™ FPGA and a Lattice-developed soft Intellectual Property (IP) core, the solution is fully compliant with the Optical Internetworking Forum's (OIF) System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1 Standard.
  
  
• Aeroflex Gaisler announces SpaceWire Router IP-Core (Monday Sep. 20, 2010)
  Aeroflex Gaisler AB, a leader in System on Chip (SoC) design, today announces the availability of a SpaceWire router IP-core. The SpaceWire router IP-core implements a SpaceWire router as defined in the ECSS-E-ST-50-12C standard. It supports from 2 to 31 ports with an additional configuration port, which can be individually configured to be external SpaceWire links, FIFO ports or AMBA ports.
  
  
• RF Engines Ltd Extends Digital RF Capabilities to Include Demodulator Cores for FPGAs (Monday Sep. 20, 2010)
  RFEL's customers who are already using RFEL's multi-channel channeliser solutions have commissioned RFEL to design demodulator cores that will facilitate the simultaneous monitoring of a large number of modulated channels. Examples include one application targeting over 50 channels in the limited resources of a single Xilinx Virtex-II FPGA, another example addressing in excess of 120 channels in a Virtex 6 device.
  
  
• Cryptography Research and IP Cores Announce Agreement for Differential Power Analysis Countermeasures Patents (Wednesday Sep. 15, 2010)
  Cryptography Research, Inc. and IP Cores, Inc. today announced an agreement which will enable IP Cores, Inc. to develop DPA countermeasure implementations for sale to licensees of Cryptography Research's DPA patents.
  
  
• Synopsys Reduces IP Integration Risk With Extensive SATA-IO Interoperability Testing (Tuesday Sep. 14, 2010)
  Synopsys today announced that Synopsys' DesignWare® Serial Advanced Technology Attachment (SATA) IP solution has successfully passed the SATA International Organization (SATA-IO) electrical, digital and system interoperability testing for 130- to 40-nanometer (nm) process technologies.
  
  
• Alvand Technologies Announces Ultra Low Power, Small Die-Area Analog-to-Digital Converter (ADC) Intellectual Property (IP) Solution in Advanced 40nm Process Node (Tuesday Sep. 14, 2010)
  Alvand Technologies announces the production-readiness of the industry’s lowest power, smallest die-area analog-to-digital converter (ADC). Designed in leading 40nm manufacturing process node, the ALVADC10_165M40THLA IP solution from Alvand is a robust 10-bit, 165 Mega-samples-per-second (MSPS) pipeline ADC that features excellent dynamic range performance, with a signal-to-noise ratio (SNR) of 56 dBFS, and high immunity to substrate noise.
  
  
• Sonics Unveils Industry's First IP Solution to Solve Memory Bottlenecks and Increase Memory Bandwidth Utilization (Tuesday Sep. 14, 2010)
  Sonics introduced MemMax AMP™, the first standalone memory scheduler that optimizes memory bandwidth/DRAM scheduling on-chip in a single IP block. MemMax AMP is the only on-chip memory IP solution that allows SoC designers and system architects to significantly boost memory bandwidth utilization from the average ~45-50 percent level up to 85 percent in some designs, without re-architecting the system design or changing the memory subsystem.
  
  
• Dolphin integration unveils a new Virtual Component for power metering (Monday Sep. 13, 2010)
  Dolphin Integration launches a new Analog Front-End, embedding all the analog functions for a single-phase power-meter: the current path, the voltage path with programmable PGA, the tampering detection path, and the voltage reference is offered as an option. This AFE is targeting first TSMC 0.18 um process but can be easily migrated towards other foundries and processes.
  
  
• Novelics Expands Its Memory IP Offering to 40nm With a Great Set of Differentiation (Monday Sep. 13, 2010)
  Novelics today announced the expansion of it’s portfolio with the addition of coolSRAM-6T embedded memory IP and MemQuest compiler which are enhanced with Novelics 3G optimizations. This IP is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs.
  
  
• Renesas Electronics Receives USB-IF Certification for its Second Generation USB 3.0 Host Controller and USB 3.0 IP Core (Monday Sep. 13, 2010)
  Renesas Electronics Corporation today announced that its latest Universal Serial Bus 3.0 (USB 3.0) xHCI (eXtensible Host Controller Interface) host controller (part number µPD720200A) and USB 3.0 intellectual property (IP) core (IP: NBU3DEVG1) have passed USB 3.0 compliance and certification testing by the USB Implementers Forum (USB-IF)
  
  
• Lancero update now supports x8 PCI Express (Monday Sep. 13, 2010)
  Microtronix today announced the release of the new Lancero. The new version targeting high bandwidth FPGA PCI Express applications now supports x8 PCI Express.
  
  
• CoreEL Launches Low Cost Audio-Video Decoder Module Product (Friday Sep. 10, 2010)
  CoreEL today launched their low cost customizable Audio-Video decoder module product and also marked their entry into the H.264 encoder arena with the demonstration of their I-Frame encoding solution. CoreEL also announced availability of a High Bit-rate H.264 Hi422 Profile decoding solution and a Multichannel decoding solution optimized for 3D applications.
  
  
• Xilinx and Coreworks Deliver Wide Range of Professional Audio Codecs, Including Dolby, for Easy Implementation With FPGAs (Friday Sep. 10, 2010)
  Xilinx and Coreworks today announced at the IBC2010 conference the first availability of a range of new Dolby audio technology and other audio codec IP cores for compressing multichannel audio in Field Programmable Gate Arrays (FPGAs).
  
  
• Xilinx and VSofts Demonstrate Low Latency Real-Time H.264/AVC-I IP Core Compression Solution for Xilinx FPGAs (Friday Sep. 10, 2010)
  Xilinx and VSofts today demonstrated the ability of VSofts' H.264/AVC-I IP core to deliver a very low latency, ITU and Panasonic AVC-Intra compliant FPGA implementation of the industry-standard codec for providing minimal delay from source to encoded video in real-time video broadcast applications.
  
  
• Allegro DVT now shipping 3rd generation H.264/MPEG-4 AVC/MVC high-definition video encoding IP core (Thursday Sep. 09, 2010)
  Allegro DVT announces the immediate availability of the 3rd Generation of its H.264/MPEG-4 AVC/MVC high- definition hardware video encoding IP. Already licensed to a major IC vendor, it offers ultra-low latency encoding and drastically improved video quality.
  
  
• ARM Unveils Cortex-A15 MPCore Processor to Dramatically Accelerate Capabilities of Mobile, Consumer and Infrastructure Applications (Thursday Sep. 09, 2010)
  ARM today introduced the Cortex(TM)-A15 MPCore processor that delivers a 5x performance improvement over today's advanced smartphone processors, within a comparable energy footprint. In advanced infrastructure applications the Cortex-A15 processor running at up to 2.5GHz will enable highly scalable solutions within constantly shrinking energy, thermal and cost budgets. The Cortex-A15 processor is available for licensing today and is targeted at manufacture in 32nm, 28nm and future geometries.