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IP / SOC Products News

• CEVA's New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs (Tuesday Sep. 07, 2010)
  CEVA today introduced the CEVA-X1643, a highly-energy efficient,1 GHz DSP core designed to boost overall chip performance for a broad range of applications including wireline and wireless communications, surveillance, portable multimedia and more.
  
  
• Barco presents innovative solution for sub-frame latency processing of single-tile JPEG 2000 images (Tuesday Sep. 07, 2010)
  Barco Silex has presented a new JPEG 2000 IP core which performs at sub-frame latency while preserving the high quality of single-tile images. Thanks to these new cores, the cumulated latency delay to encode and decode an image becomes less than one frame. In the case of HD application, the total delay can be as low as 10 milliseconds.
  
  
• Dolphin Integration Announces a complete Panoply of Memories and Standard Cells, which uniquely offer Dual Voltage capability for the 180 nm process (Monday Sep. 06, 2010)
  Dolphin Integration is the only provider to address the dynamic power consumption challenge at the architectural level with the introduction of a complete Panoply of Memories and Standard Cells, which uniquely offer Dual Voltage capability for the 180 nm process.
  
  
• RivieraWaves announced the first Bluetooth low energy qualified baseband IP (Monday Sep. 06, 2010)
  RivieraWaves announced today that it has successfully passed the Bluetooth Qualification with its Bluetooth low energy baseband Intellectual Property (IP).
  
  
• GLOBALFOUNDRIES Launches Industry's First 28nm ARM Cortex-A9 Processor Platform with Gate First High-K Metal Gate (Thursday Sep. 02, 2010)
  At today’s inaugural Global Technology Conference, GLOBALFOUNDRIES announced it has taped-out a qualification vehicle based on the ARM® Cortexâ„¢-A9 dual processor [(LSE: ARM); (Nasdaq: ARMH)], an industry first on 28nm High-K Metal Gate (HKMG) technology.
  
  
• True Circuits Announces New Line of General Purpose PLLs Optimized for Low Power, Area Sensitive and Low Cost Applications (Wednesday Sep. 01, 2010)
  True Circuits announced today the immediate availability of a new line of silicon-proven General Purpose Phase-Locked Loop (PLL) hard macros that are well suited for system clock, DDR and general purpose timing applications. The General Purpose PLL is available in a variety of TSMC and GlobalFoundries processes.
  
  
• Posedge Announces High Performance Unified Security (MACsec + IPSEC) Solution (Tuesday Aug. 31, 2010)
  Posedge has announced the availability of PE-UNISEC Soft IP Core that performs integrated MAC Security fully conforming to IEEE 802.1AE standard and IPSEC ESP protocol processing. Posedge has developed the PE-UNISEC engine leveraging its vast experience in Internet Security technologies such as MACsec, IPSEC, SSL, and high performance crypto infrastructure.
  
  
• Dolphin Integration's Panoply of Memories and Standard Cell Libraries for easing the fabrication capacity shortage (Friday Aug. 27, 2010)
  release of the SESAME Reduced Cell Stem Library uHD-BTF rel 1.2 complements the already celebrated Dolphin Integration’s High Density and Low Power optimized Panoply of Silicon IPs.
  
  
• Arasan Chip Systems First to release UHS-II PHY IP Core (Thursday Aug. 26, 2010)
  Arasan announced that it has developed the UHS-II PHY IP core, a next generation memory interface being finalized by the SD Association. Arasan, an Executive member of the SD Association, has been in deep engagement with its strategic lead customers who are productizing this interface.
  
  
• Synopsys DesignWare SATA IP Enables First-Pass Silicon Success for Global Unichip Corporation (Wednesday Aug. 25, 2010)
  Synopsys today announced that Global Unichip has achieved first-pass silicon success for its GP5080 Solid State Drive (SSD) system-on-chip (SoC) utilizing the complete Synopsys DesignWare® SATA IP solution, consisting of controller, PHY and verification IP.
  
  
• MindTree Launches Bluetooth RF IP Enabling Complete SoC Integration (Wednesday Aug. 25, 2010)
  MindTree today announced the launch of its Bluetooth RF Intellectual Property (IP) offering, designed to provide sensitivity and Interference Tolerance performance, at 1.2 V, exceeding Bluetooth specifications. The RF IP complements MindTree’s market-proven Bluetooth suite of IPs consisting of baseband controller, digital PHY (Physical Layer), stack and profiles.
  
  
• Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm Process Technology (Tuesday Aug. 24, 2010)
  
  
  
• Update: ARM7 gets 40-bit, virtualization support (Tuesday Aug. 24, 2010)
  ARM Ltd. announced extensions for virtualization and 40-bit addressing to the ARMv7a architecture, two of the key new aspects of ARM's upcoming Eagle core. The extensions aim to serve a variety of new and existing markets from digital cameras, Web-connected TVs and servers.
  
  
• Silicon Library Inc. develops SD UHS-II PHY MACRO (Friday Aug. 20, 2010)
  Silicon Library Inc. develops SD UHS-II PHY Macro. SLI ZRSLSIPSDUHS2PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface for both SDHC and SDXC
  
  
• Aizyc announces silicon proven SDIO 3.0 Host IP Core (Monday Aug. 16, 2010)
  Aizyc Technology announces silicon proven SDIO 3.0 Host IP Core, a ready to go solution for SoC designers needing an SDIO3.0 Host interface. The complete solution, along with Hardware Validation Platform is available with custom drivers to help designers concentrate on their core design and integrate the IP with minimal effort.
  
  
• Avalon's 2D FEC enables reduced chip size and increased power savings (Wednesday Aug. 11, 2010)
  Avalon is pleased to announce the availability of its 2D FEC for 40G OTN applications offering 9.3 dB of net coding gain with 7% overhead.
  
  
• Break-through in the embedded Memory market with Dolphin Integration's dual port RAMs (Friday Aug. 06, 2010)
  Dolphin’s Dual Port memories are embedding the access strip design technique, with a pending patent, resulting in two major innovations: The silicon area of Dolphin’s DpRAM is up to 50% denser than traditional DpRAM, Dolphin’s DpRAM offers a new functionality to SoC designers: the full asynchronous access.
  
  
• MoSys, Radiocomp and GDA Technologies Partner to Deliver CPRI and OBSAI Compliant Wireless SerDes IP Solution for 3G and LTE Base Station Market (Wednesday Aug. 04, 2010)
  Mosys today announced it has partnered with Radiocomp and GDA Technologies to deliver a complete end to end connectivity solution focusing on the 3GPP long term evolution (LTE) and 4G cellular base station component market. MoSys is partnering with Radiocomp to provide a complete Common Public Radio Interface (CPRI) and Open Base Station Architecture Initiative (OBSAI) solution and with GDA to provide a Serial Rapid I/O (SRIO) base-band solution.
  
  
• Synopsys and GLOBALFOUNDRIES to Develop DesignWare Interface PHY IP for 28-nanometer Technologies (Wednesday Aug. 04, 2010)
  Synopsys and GLOBALFOUNDRIES today announced an agreement to develop the Synopsys DesignWare® SuperSpeed USB (3.0), USB 2.0, HDMI 1.4 Tx and Rx, DDR3/2, PCI Express® 2.0 and 1.1, SATA 1.5/3 Gbps and 6 Gbps, and XAUI PHY IP for GLOBALFOUNDRIES' 28-nanometer (nm) "Gate First" High-k Metal Gate (HKMG) process technologies.
  
  
• Dolphin Integration announces the availability of a flexible CODEC configuration with ultra low power for providing Nomad systems (Friday Jul. 30, 2010)
  Dolphin Integration launches its prevalent configuration for portable applications, enabling power saving thanks to the ultra low power architecture from Helium2. Benefiting from a 95 dB CODEC with its own embedded regulator and many features, the whole for a small area, is now possible.
  
  
• IP Cores, Inc. Announces a MACsec (IEEE 802.1ae) Security Processor IP Core. (Thursday Jul. 29, 2010)
  IP Cores, Inc. has announced the first core of its new high-speed MACsec security processor family. MSP1 core contains a complete implementation of the MACsec security protocol as defined by the IEEE 802.1 standardization body
  
  
• Innopower Accelerate SoC Performance with 1.2GHz in 55nm (Thursday Jul. 29, 2010)
  Innopower today announced the achievement of its high-speed cell library (UHS-Lib) and SRAM (UHS-SRAM) to accelerate the processor performance with over 1.2GHz in mainstream 55nm process. With Innopower's UHS-Lib and UHS-SRAM, users can create faster and more complex SoCs optimized for high-performance without going to the next process node.
  
  
• Rambus Introduces High-Performance DDR3 Memory Controller Interface Solution for Consumer Electronics (Wednesday Jul. 28, 2010)
  Rambus today announced a high-performance, low-cost DDR3 memory controller interface solution tailored for consumer electronics. Rambus' DDR3 solution is the first to demonstrate operation in working silicon at a data rate of 1866 megatransfers per second (MT/s) in a low-cost wire bond package.
  
  
• Synopsys First to Deliver High-Performance Audio IP in 40-nm and 55-nm Process Technologies (Wednesday Jul. 28, 2010)
  Synopsys today announced the addition of the DesignWare® 96 dB Hi-Fi Audio IP in the 40-nanometer (nm) and 55-nm process technologies to its broad portfolio of high-quality audio IP solutions. Synopsys is the first IP provider to offer audio codecs, digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) in these advanced processes.
  
  
• MOSAID Showcases Solid State Drive Prototype (Wednesday Jul. 28, 2010)
  MOSAID today introduced a Solid State Drive (SSD) prototype utilizing MOSAID's innovative HyperLink NAND (HLNAND(TM)) architecture and interface. Designed by MOSAID and its development partner INDILINX, the HLNAND SSD prototype is optimized for mass storage applications, including enterprise data centers and high-performance computing environments.
  
  
• Virage Logic Continues to Broaden Semiconductor IP Offering with New Portfolio of SoC Infrastructure Solutions (Tuesday Jul. 27, 2010)
  Virage Logic today announced the further broadening of its already extensive System-on-Chip (SoC) infrastructure IP portfolio with its new Integra product line. Based on the proven technology that Virage Logic acquired from NXP in November 2009, the Integra portfolio of SoC Infrastructure IP includes advanced Multi-layer and Control networks, embedded Quality of Service (QoS) functionality as well as memory controllers for embedded SRAMs/ROMs.
  
  
• Virage Logic Expands Semiconductor IP Portfolio with Silicon-Proven SiANA(TM) Analog IP Offering (Tuesday Jul. 27, 2010)
  Virage Logic today announced the expansion of its broad semiconductor IP product portfolio with the introduction of SiANA, a new offering of silicon-proven analog IP components essential for building multimedia consumer electronics devices.
  
  
• Virage Logic's New ARC(R) Sound AS221BD Dual-Core Processor Targets Blu-ray Audio (Tuesday Jul. 27, 2010)
  Virage Logic today announced the new ARC Sound AS221BD dual-core processor for High Definition (HD) Audio System-on-Chips (SoCs) targeting Blu-ray Disc 7.1 channel 192kHz/24-bit output HD Audio processing applications.
  
  
• eMemory prevails to become the first automotive grade OTP provider to automotive IC makers (Tuesday Jul. 27, 2010)
  eMemory announces its automotive grade Neobit OTP in 0.25um node passed reliability test in 2010 Q2 and thus prevails to become the first automotive grade OTP provider to automotive IC customers.
  
  
• IP Cores, Inc. Announces an IPsec Security Processor IP Core (Monday Jul. 26, 2010)
  IP Cores, Inc. has announced the first core of its new high-speed IPsec security processor family. The new ISP1 core is a self-contained implementation of the IPsec packet encryption and authentication algorithms as defined by the IETF.