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IP / SOC Products News

• Dolphin Integration announces the availability of the HD-LP Panoply at 130 nm for reducing SoC area up to 20% (Friday Jul. 23, 2010)
  The release of this High Density and Low Power optimized Panoply of Silicon IPs is a windfall for Designers to improve the area of their SoCs up to 20% for the whole of logic.
  
  
• MoSys Tapes out Bandwidth Engine(TM) IC for Next Generation Networking Applications (Friday Jul. 23, 2010)
  MoSys has successfully taped out its Bandwidth Engine(TM) integrated circuit (IC). This first member of the MoSys Bandwidth Engine family of advanced system solutions will combine MoSys' patented 1T-SRAM(R) high-density embedded memory with its ultra high-speed 10 Gigabits per second (Gbps) SerDes interface (I/O) technology and an arithmetic logic unit (ALU).
  
  
• CEA-Leti Unveils Low-Power Reconfigurable Multicore Chip For Software-Defined Radio and Cognitive Radio (Thursday Jul. 22, 2010)
  CEA-Leti announced today that it has developed a digital baseband circuit for software-defined-radio and cognitive-radio applications that features less than 50 microseconds (µs) for full reconfiguration and multi-applications support
  
  
• SMIC and Virage Logic Extend Partnership to 40nm LL Process Technology (Thursday Jul. 22, 2010)
  Virage Logic and SMIC today announced the extension of their longstanding partnership to the 40-nanometer (nm) low-leakage (LL) process technology. Under the terms of the new agreement, SoC designers will have access to Virage Logic's SiWare(TM) Memory compilers, SiWare(TM) Logic libraries, SiPro(TM) MIPI and Intelli(TM) DDR IP on SMIC's advanced 40nm LL process.
  
  
• EnSilica's eSi-RISC embedded processors validated for Mentor Graphics' Precision Synthesis FPGA design flow (Wednesday Jul. 21, 2010)
  EnSilica has announced that it has become a partner for Mentor Graphics’ Precise-IP vendor-independent FPGA IP platform. EnSilica’s range of eSi-RISC embedded processor cores and eSi-Comms library of communications IP has been fully validated for use in Mentor Graphics’ Precision Synthesis FPGA design flow.
  
  
• POSEDGE announces Industry's Smallest and Fastest SDIO 3.0 Device Controller (Wednesday Jul. 21, 2010)
  Posedge has announced the availability of soft IP core that performs Secure Digital IO (SDIO) device functionality. The PE-SDIOD3.0 is highly configurable and is fully compliant with the latest SDIO specification version 3.0. The Core supports SPI, SD1, and SD4 bit transfer modes for Non-embedded applications and 8bit transfer mode for embedded applications.
  
  
• Faraday Introduces 1GHz Performance ARM v5 Compliant Processor - FA726TE (Tuesday Jul. 20, 2010)
  Faraday Technology today announced its highest-performance ARM v5 instruction set architecture-compliant processor-FA726TE. The first hard core which reaches 1 GHz clock rate at the worst case is in UMC 55nm process, and the engineering sample is available now for customers' evaluation.
  
  
• Actel's CorefIR v4.0 Delivers Configurable Digital Filter Generation for Rtax-DSP with On-Chip Math Blocks (Monday Jul. 19, 2010)
  Actel today announced CoreFIR v4.0, leveraging the embedded radiation-tolerant multiply-accumulate blocks provided in Actel's recently qualified RTAX-DSP FPGAs
  
  
• CoreFFT v4.0 Now Available for Actel's RTAX-DSP FPGAs (Monday Jul. 19, 2010)
  Actel today announced CoreFFT v4.0, an intellectual property (IP) core providing Fast Fourier Transform (FFT) capabilities to DSP solutions in high reliability, radiation-tolerant spaceflight applications.
  
  
• RF Engines' Wideband Digital Down Converter efficiently processes 1 GHz bandwidth (Monday Jul. 19, 2010)
  RF Engines Limited (RFEL) has extended the range of its Digital Down Converter (DDC) technology so that it can now process up to 1 GHz of bandwidth (2Gsps ADC rate) input and provide a narrower band output. This technology can operate with fixed frequencies and bandwidths or be fully flexible as required.
  
  
• Kaben Wireless Silicon anounces Silicon-proven 0.35-0.5 ps Programmable Clock Source IP (Monday Jul. 19, 2010)
  Kaben Wireless Silicon announced today that it has successfully produced a programmable precision clock source for the timing market ideal for applications such as networking, SONET, 10G Ethernet, base stations and other telecom infrastructure.
  
  
• Aeroflex Gaisler announces MIL-STD-1553B IP-Core (Friday Jul. 16, 2010)
  Aeroflex Gaisler AB, a leader in System on Chip (SoC) design, today announces the availability of a MIL-STD-1553B IP-core. The MIL-STD-1553B IP-core includes Bus Controller (BC), Remote Terminal (RT) and Monitor (MT) and configures as either a BC/RT/MT or RT only. The MIL-STD-1553B is available for licensing either as a part of the GRLIB IP library or as a separate IP-core in VHDL source code.
  
  
• MoSys and Northwest Logic Offer Integrated PCI Express and DDR3 Solutions (Wednesday Jul. 14, 2010)
  MoSys and Northwest Logic offer integrated PCI Express 2.0® and DDR3 solutions. The PCI Express 2.0 solution combines MoSys’ PHY for PCI Express 2.0 and Northwest Logic’s full-featured Expresso 2.0 Core, DMA Back-End Core, DMA Driver and Expresso GUI to provide a complete, pre-packaged PCI Express 2.0 solution. The DDR3 solution combines MoSys’ DDR3 PHY and Northwest Logic’s high-performance DDR3 SDRAM Controller Core and add-on cores (AXI/AHB, Multi-Port, Reorder, etc.).
  
  
• Intilop's TCP/IP Offload engine provides lowest latency and fastest TCP/IP throughput (Wednesday Jul. 14, 2010)
  Intilop’s TCP/IP Offload engine (TOE Engine) is proven provide lowest latency and fastest TCP/IP throughput among the available TOE engines in the market today. The performance validation was independently performed by a major worldwide Japanese Securities company with offices in USA.
  
  
• Avalon and AppliedMicro Enable Efficient 100G Muxponder Applications (Tuesday Jul. 13, 2010)
  Avalon Microelectronics today announced the development of a 100G GMP adaptation application to interface with AppliedMicro's Yahara 10G Framer/Mapper/PHY device.
  
  
• Silicon Image Introduces New RAID IP Core Based on Production-Proven SteelVine(R) Technology (Tuesday Jul. 13, 2010)
  Silicon Image today announced the availability of a new IP core based on its SteelVine (R) Series 3 Core technology for SATA storage processors. The IP core is a low-cost solution supporting RAID0, RAID1 and JBOD for consumer electronics (CE) storage applications.
  
  
• Algotronix announces an XTS-AES IP core for storage applications (Tuesday Jul. 13, 2010)
  Algotronix Ltd., Edinburgh, UK announces the availability of an XTS-AES core to meet the NIST SP800-38E recommendation published in January 2010 and the IEEE 1619-2007 standard.
  
  
• Arithmetic Processing IP Core for MP3 Decoders Feature Smallest Circuit Size and Lowest Power Consumption (Monday Jul. 12, 2010)
  Murata Manufacturing Co., Ltd., in collaboration with Mathematec Corporation, has developed an arithmetic processing IP core for MP3 decoders that uses less than 10% of the power required for conventional general software processing.
  
  
• Dolphin Integration offers a cutting-edge solution for the smooth integration of a precise measurement Converter into a soC (Friday Jul. 09, 2010)
  Dolphin Integration extends their pursuit of reactivity for releasing fast and safe custom configurations for High Resolution Analog Front-Ends for Sensors. To this end, they had launched the configurator JAXSENS of a kit of pre-designed mixed-signal blocks.
  
  
• IP Cores, Inc. Ships a High-Speed Forward Error Correction (FEC) IP Core (Thursday Jul. 08, 2010)
  IP Cores, Inc. has shipped the first core of its new high-speed forward error correction (FEC) IP core family. The CEC1 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the section 74 IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation).
  
  
• eMemory announces industry's first and only Green High Density OTP solution (Wednesday Jul. 07, 2010)
  eMemory today announces the industry’s first and only 0.18um/3.3V Green High Density OTP solution as an enthusiastic and immediate response to the semiconductor industry’s recent call for green energy and environmental protection.
  
  
• Lattice and Helion Provide Full HD HDR Color Pipe for Video Security & Surveillance Applications on Lattice FPGA Families (Tuesday Jul. 06, 2010)
  Lattice and Helion today announced that they have released IP cores for the video security and surveillance camera market. Targeting the LatticeXP2(TM), LatticeECP2M(TM) and LatticeECP3(TM) FPGA families, Helion has demonstrated its IONOS video pipeline IP and Vesta evaluation platform.
  
  
• IP Cores, Inc. Ships Compression/Encryption Combo IP Core (Monday Jul. 05, 2010)
  IP Cores, Inc. has shipped first member of its new high-speed lossless data compression / encryption IP core family.
  
  
• Sundance introduces its latest OFDM FPGA IP core based on 802.11a/g/n (Monday Jul. 05, 2010)
  Sundance Digital Signal Processing today introduced its latest FPGA IP core, code named FC300, which is a complete implementation of an OFDM physical layer, based on 802.11a/g/n.
  
  
• Virage Logic Continues to Broaden Semiconductor IP Offering With New Portfolio of Production Proven Processor Peripheral Cores (Wednesday Jun. 30, 2010)
  Virage Logic today announced the further broadening of its already extensive semiconductor IP product offering with the introduction of a new portfolio of processor peripheral IP including UART, USART, GPIO, SPI, I2C, General Purpose Timer, and Watchdog Timer cores.
  
  
• TSMC Announces Automotive Qualified 0.25-Micron One-Time-Programmable IP (Wednesday Jun. 30, 2010)
  TSMC today announced that its 0.25-micron One-Time-Programmable (OTP) IP now meets Automotive Electronics Council (AEC) standard AEC-Q100 specification.
  
  
• Development of Close Proximity Wireless Technology with Integrated On-Chip Antenna (Tuesday Jun. 29, 2010)
  Renesas today announced the development of new technology that realizes a close proximity wireless communication over very short distances of a few centimeters, in which a compact antenna only a few square millimeters in area (about one-hundredth the area of conventional antennas) can be integrated with the transmitter and receiver circuit blocks in a single chip.
  
  
• SMSC's High Speed Inter-Chip (HSIC) USB4640 Available (Monday Jun. 28, 2010)
  SMSC today announced that its High Speed Interconnect (HSIC) USB4640, a USB 2.0 hub plus Flash Media Reader combo device is available now. HSIC, which incorporates SMSC's patented Inter-Chip Connectivity (TM) (ICC) technology, enables silicon devices, System in Package (SIP) solutions and Multi-Chip Modules (MCM) connected on a circuit board utilizing the ubiquitous USB 2.0 protocol.
  
  
• Dolphin Integration introduces a new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10% (Friday Jun. 25, 2010)
  The Dolphin Integration High Density Panoply for the 65 nm technological process comprises a complete solution for the whole logic design to address the cost reduction challenge at the architectural level.
  
  
• Tensilica HiFi Audio DSP Becomes First IP Core Approved for Dolby MS10 Multistream Decoder (Wednesday Jun. 23, 2010)
  Tensilica today announced that it is the first IP company with an audio core for SOC designs approved for using the Dolby MS10 Multistream Decoder, a multi-format audio decoding technology, that supports Dolby Digital Plus and Dolby Pulse in a single package for next-generation HDTVs, STBs and DMPs.