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IP / SOC Products News

• IP Cores, Inc. Ships High-Speed Lossless Compression Core (Tuesday Jun. 22, 2010)
  IP Cores Announces Another Shipment of a High-Speed Lossless Data Compression IP Core. LZR1 implements the lossless compression algorithm on short units of data (“frames”).
  
  
• Arasan Chip Systems Announces highly integrated 10G Ethernet MAC IP Core (Tuesday Jun. 22, 2010)
  Arasan announced the release of its 10 Gigabit Ethernet MAC IP core. 10 Gigabit (10G) Ethernet boosts network bandwidth, thereby enabling the delivery of next generation applications over a common Ethernet platform.
  
  
• CAST H.264 Video Encoder IP Core Now More Flexible, Faster, and Easier to Integrate (Monday Jun. 14, 2010)
  An improved H.264 Encoder Core just released by CAST helps video system designers use advanced H.264 video compression for more applications, in economical smaller FPGAs, and with fewer system integration challenges than previously possible.
  
  
• CebaTech Adds Multi-Stream GZIP and GUNZIP Protocol for Data Networking Applications (Monday Jun. 14, 2010)
  CebaTech has announced the expansion of its CebaRIP library of rapidly tunable silicon intellectual property (IP) cores with new, multi-stream versions of its GZIP compression and GUNZIP decompression IP targeted specifically at data networking applications.
  
  
• Dolphin Integration introduces an ultra High Density Library decreasing the 130 nm logic area up to 30% (Friday Jun. 11, 2010)
  Designers of cost-optimized SoC designs can rely upon the highest-density Standard Cell Library, HD-BTF to improve the area of their logic blocks with a decrease up to 30%.
  
  
• ASICS World Services Achieves Compliance Certification for it's SATA Host IP Core (Friday Jun. 11, 2010)
  SICS World Services, Ltd. is proud to announce that it is one of the first companies to achieve Compliance Certification for it's SATA Host IP Core. The SATA I/II/III Host Controller IP Core is a full featured SATA Host controller, that provides auto-speed negotiation, various power modes, as well as native and legacy software interfaces.
  
  
• Innopower First to Deliver Complete Memory Compiler and Miniaturized Cell Library, miniLib+, for 55nm LP(Low Power) process (Thursday Jun. 10, 2010)
  Innopower Technology today announced the availability of the miniaturized cell libraries, miniLib+™, and memory compilers for the industrial-standard 55nm LP(low-power) process. The new products provide IC design houses with 55nm IPs that is designed to enable SoC to have better power consumption, smaller die area, and higher manufacturing flexibility.
  
  
• Imagination demonstrates latest Stereoscopic 3D (S3D) graphics and display technologies (Thursday Jun. 10, 2010)
  Imagination Technologies is demonstrating implementations of its licensable 3D, Video and Display IP technologies capable of delivering immersive stereoscopic 3D (S3D) experiences.
  
  
• Imagination Technologies announces POWERVR SGX544MP multi-processor graphics IP (Thursday Jun. 10, 2010)
  Imagination Technologies announces POWERVR SGX544, a high performance graphics core for embedded and mobile applications with full support for Microsoft DirectX 9 and multi-processor capability.
  
  
• MoSys and CEVA Partner to Deliver Integrated SATA 3.0 PHY and Controller IP Solution (Wednesday Jun. 09, 2010)
  MoSys and CEVA have partnered to deliver a joint PHY plus Controller solution for SATA 3.0, for both Host and Device side applications. The combined solution unleashes the full potential of embedding 6Gbps SATA interfaces in next generation products by leveraging MoSys' 6Gbps SerDes PHY and CEVA's SATA 3.0 Controller IP.
  
  
• Innovision Research & Technology makes next-generation GEM NFC IP available for licensing (Wednesday Jun. 09, 2010)
  Innovision Research & Technology has made version 2 of its GEM NFC (Near Field Communication) semiconductor technology available for licensing – further opening up the market for any semiconductor company to integrate NFC into chipsets for mobile phones and consumer electronics devices.
  
  
• Menta and LIRMM Launch Manufacturing of World's First RAM-based FPGA (Wednesday Jun. 09, 2010)
  Menta SAS and LIRMM today confirmed the tape out of world’s first MRAM-based FPGA. The MRAM-based FPGA leverages key innovations including non-volatile magnetic memory and patent-protected circuitry enabling compact integration of MRAM and embedded-FPGA solutions.
  
  
• Cyclic Design Announces Enhanced BCH ECC Portfolio: G14X IP Supports 64-bit Error Correction for NAND Flash Applications (Wednesday Jun. 09, 2010)
  Cyclic Design announces the G14X BCH ECC IP that extends the existing G14 IP to enable support for up to 64 corrections per correction block. The IP ensures that licensees have the flexibility to increase ECC strength in NAND Flash interfaces for future generation flash devices.
  
  
• Imec's cognitive baseband radio to support 4G and broadband access to multiple services (Tuesday Jun. 08, 2010)
  Imec introduces a cognitive baseband radio (COBRA) architecture targeting 4G requirements at up to 1Gbit/s throughput and multiple asynchronous concurrent streams (for instance simultaneous digital broadcasting reception and high-speed internet access)
  
  
• Evatronix Facilitates Its JPEG 2000 Encoder Evaluation with the Online Demo Application (Tuesday Jun. 08, 2010)
  Evatronix SA, announced today the introduction of an online application that demonstrates the capabilities of the company’s JPEG 2000 Encoder IP core. This free demo system is easily accessable through the Evatronix website.
  
  
• CAST 80251 Processor IP Core Runs Legacy and New Code Up to 24x Faster (Tuesday Jun. 08, 2010)
  Electronic designers using the popular 8051 microcontroller can now apply their investment in 8051 knowledge and code to faster systems using the R80251XC IP core from CAST, Inc.
  
  
• Chips&Media adds VP8 on its new BODA9 / CODA9 (Tuesday Jun. 08, 2010)
  Chips&Media today announces that it will include VP8 in its the latest video codec IP family, BODA9™/CODA9™, high performance 1080p 60fps HD video decoder IP cores with multi-format capabilities.
  
  
• PLDA Furthers Its PCIe Industry Leadership with the Introduction of the World's First PCI Express 3.0-Based IP for ASIC and FPGA (Monday Jun. 07, 2010)
  PLDA today announced the immediate availability of XpressRich3 - the world’s first IP core for leading FPGAs and ASICs based on the forthcoming PCIe® 3.0 specification, currently under development within the PCI-SIG®. The PLDA XpressRich3 core features an innovative architecture that seamlessly allows both ASIC and FPGA implementations, an extensive list of configurable features and a broad range of user interface options to easily achieve simple to more complex design requirements.
  
  
• Sidense Introduces Ultra-Low-Power NVM Memory (Monday Jun. 07, 2010)
  Sidense today announced the introduction of the Company’s ULP (Ultra-Low Power) one-time programmable (OTP) macro family. ULP macros are based on the Company’s patented one-transistor (1T) split-channel architecture (1T-Fuse™) and require no additional masks or process steps, thus adding no extra wafer processing cost.
  
  
• Actel Delivers Free IP Cores Bundle and RTL Package Option with Standard Software Packages (Monday Jun. 07, 2010)
  Actel is making it easier to build powerful designs using the proven IP blocks in its portfolio by including free access to IP libraries in its Libero® Gold edition and RTL-source IP libraries in its Libero Platinum edition. Access to more than fifty IP cores is now included in the comprehensive software toolset.
  
  
• MoSys and Sarance Partner to Deliver Complete 40 Gigabit and 100 Gigabit Ethernet and Interlaken Solutions (Thursday Jun. 03, 2010)
  MoSys and Sarance have partnered to deliver joint PHY plus Media Access Controller (MAC) solutions supporting 40 Gigabit Ethernet, 100 Gigabit Ethernet and Interlaken specifications. The combined solution leverages MoSys' 10Gbps SerDes and Sarance's 40GE and 100GE MAC, Physical Coding Sub-layer (PCS) and Multi Lane Distribution (MLD) IP conforming to the emerging 40GE and 100GE standard using IEEE defined XLAUI (40GE) and CAUI (100GE) interfaces.
  
  
• Virage Logic Introduces New Sonic Focus(R) PC Audio Enrichment IP (Thursday Jun. 03, 2010)
  Virage Logic today announced that ASUSTeK Computer has licensed Virage Logic's new Sonic Focus PC audio enrichment IP. The entire line of Sonic Focus(R) audio software, including the new Sonic Focus PC, will ship on the new ASUS N43, N53, NX90 and N73 notebooks as part of ASUS' exclusive SonicMaster audio suite--a raft of hardware and software enhancements developed in collaboration with Bang & Olufsen ICEpower(R).
  
  
• Kilopass Announces Industry's Largest Embedded Logic Non-Volatile Memory for Leading-Edge Semiconductor Systems-on-Chip (Wednesday Jun. 02, 2010)
  Kilopass Technology unveiled a one-time programmable 4-Mb non-volatile memory IP product large enough to store the firmware and boot code that is traditionally stored in external serial-flash EEPROM chips.
  
  
• Cosmic Circuits announces silicon-proven 40nm Wireless Analog IP (Monday May. 31, 2010)
  Cosmic Circuits today announced the availability of a silicon-proven platform of mixed-signal IP cores in TSMC 40nm for wireless communications applications, resulting from its collaboration with TSMC.
  
  
• Dolphin Integration adds a Sample Rate Converter to its audio converter (Friday May. 28, 2010)
  The frequent nightmare of Audio/Video system designers is the synchronization of audio data with different streams. The recourse to one or more PLL’s not only is at risk of complex jitter issues but its solution in any case is painful. What is more such complexity prevents from foreseeing the actual impact on audio performance.
  
  
• Digital Imaging Core Now Available for Integration From DarbeeVision (Thursday May. 27, 2010)
  DarbeeVision today announced the availability of its patented Visual Presence(TM) IP core, the DV3000. The DV3000 uses innovative technology which inserts depth cues to create images that seem to pop off the screen -- enabling a visual experience where the viewer is immersed into a two-dimensional world with incredible depth and lifelike images.
  
  
• CAST Reference Design System Simplifies H.264 Video Compression Evaluation and Analysis (Tuesday May. 25, 2010)
  Electronic system design engineers who need to understand and evaluate H.264 video encoding now have a quick, cost-effective, ready-to-run tool for doing just that. The H.264 Video Encoding Reference Design System from CAST, Inc. combines multiple hardware functions and essential software in a pre-integrated, well-documented package. The System is available now, running in either Altera or XIlinx FPGAs on commercial prototyping boards.
  
  
• SMIC and Virage Logic Expand Partnership to Offer Virage Logic's IP on SMIC's 65nm LL Process (Monday May. 24, 2010)
  Virage Logic and SMIC today announced the expansion of their longstanding partnership to include the 65-nm low-leakage (LL) process technology. Under the terms of the agreement, System-on-Chip (SoC) designers will have access to Virage Logic's SiWare Memory compilers, SiWare Logic libraries, SiPro MIPI and Intelli DDR IP on SMIC's 65nm LL process.
  
  
• Evatronix Introduces an Ultra-fast Intel 80C251 Compatible Microcontroller IP Core (Monday May. 24, 2010)
  Evatronix today announced the R80251XC – the high performance 32-bit Intel 80C251 compatible microcontroller. It is the ultimate 8051 compatible IP core, with performance results that exceed these of the original Intel 8051 chip by more than 24 times, which translates to over 3 times better result than the Intel 80C251 at the same clock frequency.
  
  
• Innopower Technology Corp. Announces the Availability of USB 3.0 Physical Layer (PHY) IP Which Has Passed USB-IF SuperSpeed Certification, through Customers' Solutions (Monday May. 24, 2010)
  Innopower Technology announced today the availability of the USB 3.0 PHY IP from Faraday Technology, which has successfully passed USB-IF (USB Implementers Forum) SuperSpeed certification and obtained the compliance logo through the customer products for both host and device ends.