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IP / SOC Products News

• Evatronix Optimizes its I2S Audio Interface Controller by Adding TDM Support and Single Channel Operation (Monday Mar. 15, 2010)
  Evatronix SA, announced today the introduction of the I2S-SC controller IP. It is compatible with the Philips I2S specification and all its modes; however, it reduces the number of supported channels from eight to one and introduces the Time Division Multiplexing (TDM) mechanism for more efficient multi-channel handling.
  
  
• Tensilica Introduces Third Generation Diamond Standard Controllers Optimized for Low Power, High Performance Applications (Monday Mar. 15, 2010)
  Tensilica today introduced its third generation of Diamond Standard controllers. Improvements in this third generation of Diamond Standard controllers deliver up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power consumption.
  
  
• Noesis Technologies releases fully configurable N-point FFT/IFFT core (Friday Mar. 12, 2010)
  Noesis Technologies announced today the immediate availability of its N-point fully configurable FFT/IFFT core (ntBFFT). ntBFFT core is a fully configurable solution that performs the FFT and IFFT transform. It is on-the-fly programmable in terms of transform size and type. It supports complex input/output and the results are output in normal order.
  
  
• Sonics Announces Support for AMBA 4 Specification (Thursday Mar. 11, 2010)
  Sonics, Inc.®, announced that its on-chip communications solutions will support phase one of the new AMBA® 4 protocol unveiled this week by ARM. This ensures that chip designers who currently use the AMBA 3 specification will have an easy migration path to AMBA 4 products as design upgrades are rolled out. ARM indicates further enhancements to the specification will be available later this year.
  
  
• Silicon Hive Introduces HiveLogic Configurable Parallel Processing Platform (Wednesday Mar. 10, 2010)
  Silicon Hive today announced HiveLogic, a configurable parallel processing platform enabling embedded programmable solutions for system-on-chips at unprecedented silicon area utilization and power consumption efficiency. The underlying parallel processing technology has already been deployed by Silicon Hive in mass-consumer solutions for connected multimedia applications in smart phones and digital televisions.
  
  
• POSEDGE announces Ultra Speed, High Performance, and Low Gate Count SD/SDIO/eMMC Host Controller IP (Tuesday Mar. 09, 2010)
  Posedge has announced the availability of soft IP Core that performs SD/SDIO/eMMC Host controller functionality. The Posedge SD/SDIO/eMMC Host Controller Core is highly configurable and is compliant with SD Host 3.0, SDIO 3.0, and eMMC4.4 specification.
  
  
• Altera's Stratix IV FPGAs Pass Interlaken Interoperability Test (Monday Mar. 08, 2010)
  Altera today announced its Stratix® IV FPGAs passed the Interlaken Alliance's device interoperability testing. Altera passed interoperability testing using a Stratix IV GT FPGA development board along with Altera's internally developed Interlaken intellectual property (IP) core.
  
  
• CSEM introduces a new generation of ultra low power DSP RISC cores for portable applications (Tuesday Mar. 02, 2010)
  The icyflex family of ultra low power 16/32-bit RISC processor cores developed by CSEM, the Swiss Center for Electronics and Microtechnology, offers a flexible ar-chitecture that allows for different combinations of control and DSP functionality. Three silicon-proven cores are so far available, consuming as little as 6 μW/MHz.
  
  
• Crack Semiconductor Releases Performance Data For The CS256-ECC and CS1024-PKA Processors (Tuesday Mar. 02, 2010)
  Crack Semiconductor's CS256-ECC and CS1024-PKA processors offer amazing performance for GF(p) Elliptic Curve operations up to 512-bits based. . The CS256-ECC is a smaller, ECC-only variant of the CS1024-PKA processor with the same ECC performance.
  
  
• iSine Inc. Releases Extreme ECC(tm) for NAND Flash SOC's optimized for ASIC and Xilinx FPGA implementation (Tuesday Mar. 02, 2010)
  iSine Inc. has announced the full release of its Extreme ECC technology that meets the needs of the most demanding error correction environments. The Extreme ECC technology supports traditional SLC and MLC NAND Flash requirements, in addition to Standard ONFI 2.1 and Toggle Mode NAND Flash interface demands.
  
  
• Noesis Technologies releases NIST FIPS-197 compliant Low Power AES IP core (Monday Mar. 01, 2010)
  Noesis Technologies announced today the immediate availability of its NIST FIPS-197 compliant Advanced Encryption Standard IP core (ntAES8). ntAES8 core can be programmed to encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key.
  
  
• Dolphin Integration widens their catalog with libraries targeting both Low Power and High Speed (Monday Feb. 22, 2010)
  In 2010, Dolphin Integration focuses their product offering on both their long-established know-how on Low Power designs for embedded memories and standard cell libraries. New architectures are released from the 130 nm technological process down to 40 nm LP with versions optimized for high speed.
  
  
• ARM Launches Class-Leading Cortex-M4 Processor For High Performance Digital Signal Control (Monday Feb. 22, 2010)
  ARM today announced the launch of the innovative Cortex™-M4 processor to provide a highly efficient solution for digital signal control (DSC) applications, while maintaining the industry leading capabilities of the ARM® Cortex-M family of processors for advanced microcontroller (MCU) applications.
  
  
• SiliconGate Introduces the First Ultra Fast DC/DC IP for Process Technologies Ranging from 0.25um to 40nm (Friday Feb. 19, 2010)
  SILICONGATE today announced the availability of silicon-proven SGC67120, the first in a family of synchronous step-down DC/DC converters designed to operate from a 1.8V to 5.5V input and deliver up to 3A to 0.6V to 3.6V outputs. With an extremely fast 1.5µs response time, this new converter promises to reduce the external capacitor size and overall solution cost for portable applications.
  
  
• SoftJin announces High Performance JPEG Encoder and Decoder IP (Thursday Feb. 18, 2010)
  SoftJin announces JPEG Encoder and Decoder IP. SoftJin’s JPEG encoder IP is a high performance RTL solution and capable of encoding Still Images as well as Video stream with SD, VGA and HD resolution.
  
  
• Elliptic Technologies Offers Solution to Longstanding Security challenge - implementing asymmetric or public key cryptography (Tuesday Feb. 16, 2010)
  Elliptic today announced that it has released a comprehensive solution to perhaps the most difficult challenge today facing designers in security – implementing asymmetric or public key cryptography.
  
  
• Intelop corporation's TCP Offload engine IP delivers amazing TCP/IP throughput (Tuesday Feb. 16, 2010)
  Intelop corporation’s TCP Offload engine IP delivers amazing TCP/IP throughput as reported by customers in system level performance testing. This second generation Customizable Full TCP offload Engine also integrates GEMAC, ARP module, RDMA engines, PLB/405 bus interfaces running at 2-Gbps. It is capable of implementing/ accelerating hundreds of simultaneous TCP sessions, delivering 800 % -1500% performance improvement over TCP/IP software implementations.
  
  
• Imagination extends standards supported on ENSIGMA UCCP310 with Wi-Fi and ATSC, demonstrates SoC test chip (Monday Feb. 15, 2010)
  Imagination Technologies is demonstrating two of Imagination's latest ENSIGMA UCCP310 IP platforms running real time Wi-Fi and ATSC integrated on an advanced SoC test chip at MWC 2010 in Barcelona (15-18 February 2010).
  
  
• CEVA Unveils Industry's First Multipurpose Programmable HD Video and Image Processing Platform for Connected Multimedia Devices (Monday Feb. 15, 2010)
  CEVA today unveiled CEVA-MM3000™, a fully programmable, HD video and imaging platform specifically designed for the connected generation of portable multimedia and home entertainment devices.
  
  
• ArrayComm and CEVA Partner to Develop LTE Wireless Infrastructure Solution (Friday Feb. 12, 2010)
  ArrayComm and CEVA today announced an agreement to work toward the implementation of ArrayComm’s full LTE eNodeB PHY on the CEVA-XC™ DSP core. This will provide SoC product developers with a pre-optimized PHY software/processor package to incorporate in their overall system design.
  
  
• Blue Wonder Communications Uses 4M Wireless LTE Protocol Stack to Complete LTE Reference Platform (Friday Feb. 12, 2010)
  Blue Wonder has integrated its LTE baseband solution with the 4M Wireless LTE protocol as part of a complete LTE terminal reference platform.
  
  
• Silicon Hive announces World's First Programmable Digital Radio Frequency Processor for Smart Phones (Thursday Feb. 11, 2010)
  Silicon Hive announces HiveFlex CSP2500 Digital RF Processor. The silicon-proven CSP2500 processor enables fully C-programmable, multi-standard smart phone transceiver platforms targeting EDGE, UMTS, LTE, cdma2000, WiFi and WiMAX technologies.
  
  
• Eureka Technology Supports PLB Bus Interface for Most of Its Popular IP Cores (Thursday Feb. 11, 2010)
  Eureka Technology today announces the availability of the CoreConnect™ PLB™ Bus interface option for most of its IP core products. PLB Bus is the native interface standard for PowerPC and Power Architecture-based embedded processors and the Xilinx MicroBlaze™ CPU. By supporting the PLB™ bus interface standard, Eureka’s IP cores can be integrated seamlessly with any SoC design based on these standard CPU cores.
  
  
• Athena Delivers Powerful 3GPP LTE Multi Radix FFT Processor Core (Wednesday Feb. 10, 2010)
  The Athena Group today announced the general availability of its multi-radix FFT core for LTE and other OFDM-based wireless communications. The PFFT-M for LTE delivers the throughput needed for basestation LTE downlink OFDMA as well as the flexibility to handle the complexity of LTE uplink SC-FDMA in a single core.
  
  
• IPextreme and Globetech Solutions Announce Availability of Industry's First Complete IEEE 1149.7 cJTAG IP Solution (Wednesday Feb. 10, 2010)
  IPextreme and Globetech Solutions today announced the availability of the electronics industry's first complete IEEE 1149.7 cJTAG IP solution. The solution, comprising IPextreme's cJTAG silicon IP (SIP) and Globetech's cJTAG verification IP (VIP) products, will help system designers quickly and easily take advantage of the many performance and cost saving features of the 1149.7 standard.
  
  
• Imec and Holst Centre present ADC with record figure of merit suited for low energy radios (Wednesday Feb. 10, 2010)
  Imec and Holst Centre report an ultra-low power 8 bit analog to digital convertor (ADC) consuming only 30fJ energy per conversion step. This world-class figure of merit ADC is especially suited for upcoming low energy radios in the ISM (industrial, scientific and medical) radio bands such as low-energy Bluetooth or IEEE 802.15.6 for body-area networks.
  
  
• Imec, Renesas and M4S report a single-chip reconfigurable multi-standard wireless transceiver in 40nm CMOS (Wednesday Feb. 10, 2010)
  The fully reconfigurable transceiver is compatible with various wireless standards and applications, including the upcoming mobile broadband 3GPP-LTE standard.
  
  
• Rambus Unveils Mobile XDR Memory for Next-Generation Mobile Products (Monday Feb. 08, 2010)
  Rambus today unveiled its Mobile XDR(TM) memory architecture for next-generation mobile products. Mobile XDR memory offers a high-bandwidth, low-power memory architecture to enable devices that exceed the power and performance targets for next-generation mobile products.
  
  
• Tensilica Introduces Second Generation ConnX BaseBand Engine DSP for Demanding Algorithms for LTE/4G Wireless Handsets and Base Stations (Monday Feb. 08, 2010)
  Tensilica today introduced ConnX BBE16, its second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. ConnX BBE16's 16-way MAC (multiply accumulator) architecture is optimized for the most demanding wireless DSP (digital signal processing) tasks, including OFDM (Orthogonal Frequency-Division Multiplexing) algorithms and FFT (Fast Fourier Transform), FIR (Finite Impulse Response), IIR (Infinite Impulse Response), and matrix computation.
  
  
• IP Cores, Inc. Announces a Family of Low-Latency AES/GCM IP Cores Supporting IEEE 802.11ad and WiGig Standards (Thursday Feb. 04, 2010)
  IIP Cores, Inc. Announces a New Low-Latency Family of Silicon IP Cores Supporting the GCM-AES Mode as Defined by the NIST Publication SP800-38D and Used by Wireless Communication Standards IEEE 802.11ad and WiGig. Starting at 64K ASIC Gates and Throughput of 20 Gbps for the Low-End GCM5-32 Core, GCM5 Family of Cores Provides an Efficient Encryption Solution for an SoC Designer that Has to Work with Very Short Communication Data Packets and Multi-Gigabit per Second Data Rates.