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IP / SOC Products News

• TranSwitch to Unveil Latest High Definition Video Interconnect Technology at 2010 International CES (Monday Jan. 04, 2010)
  TranSwitch will formally introduce its latest High Definition Multimedia Interface™ (HDMI) for next generation digital television (DTV) and home theatre applications at the 2010 International CES trade show. The HD-PXL™-1.4 includes 3D Video and support for new 4K super resolution displays.
  
  
• Digital Blocks Supports the AMBA Interconnect on Xilinx FPGAs with its portfolio of AXI / AHB / APB IP Cores (Wednesday Dec. 30, 2009)
  Digital Blocks today announces its support of the AMBA® Interconnect on Xilinx® FPGAs with Digital Blocks Peripheral IP cores.
  
  
• Ukalta Engineering Announces Ultra-Compact AWGN IP Library (Tuesday Dec. 22, 2009)
  Ukalta Engineering today announced the commercial availability of its Gaussian noise generator Intellectual Property (IP) cores. With the smallest footprint, best accuracy and highest throughput currently available on the market these IP cores provide an ideal solution for bit-error rate testing of communication systems over additive white Gaussian noise (AWGN) channels.
  
  
• Silicon Image Introduces New 4K and 3D H.264 Digital Video Decoder IP Core (Tuesday Dec. 15, 2009)
  Silicon Image today announced the newest member of its IP core family, the cineramIC™ 4K and 3D H.264 digital video decoder. With its high performance, low cost and high-quality video imaging, the cineramIC IP core can be integrated into System-on-Chips (SoCs) for next-generation digital TV (DTV), set-top-box (STB) and camcorder applications, as well as professional video editing, broadcast, medical and surveillance FPGA applications.
  
  
• Arasan Chip Systems Announces Innovative SD 3.0 / eMMC 4.4 Card Controller IP (Tuesday Dec. 15, 2009)
  Arasan announced today the availability of the World's first SD 3.0 / eMMC 4.4 Card Controller IP compliant with the latest SD Memory v3.0 and Multimedia Card eMMC 4.4 specifications. Arasan's Card Controller IP supports transfers up to 104MB/s and incorporates all standard security features.
  
  
• Virage Logic Introduces the Ultra Compact and Low Power ARC(R) 601 32-Bit Microprocessor Core (Tuesday Dec. 15, 2009)
  The ARC 601 Offers a Remarkable Combination of Small Size, Lower Power and Outstanding Performance for Embedded and Microcontroller Applications
  
  
• Crack Semiconductor's CS1024-RSA Sets New RSA Compute-Offload Performance Standard (Tuesday Dec. 15, 2009)
  Crack Semiconductor announces today that its RSA compute offload engine, the CS1024-RSA, has demonstrated a measured performance of at least 177 RSA-1024 full exponent 1024-bit operations per second in a 32-bit Silicon IP core.
  
  
• CEVA and Gennum's Snowbush IP Group Partner to Deliver Complete SAS 2.0 IP Solution for Embedded Storage Applications (Monday Dec. 14, 2009)
  CEVA and Snowbush today announced that they have partnered to deliver a complete Serial Attached SCSI (SAS) 2.0 IP solution optimized for embedded storage applications. The integrated offering combines Snowbush silicon-proven 6.0Gbps PHY IP integrated with CEVA's SAS 2.0 Controller IP, offering the industry's most mature and feature rich SAS 2.0 IP solution.
  
  
• Avalon Announces Working 100GE over OTN Transponder Application (Thursday Dec. 10, 2009)
  Avalon is pleased to announce our first working 100GE over OTN transponder application, using our industry-leading Zenobia Virtual Application-Specific Standard Product (V-ASSP) in conjunction with the "Cobra" 100G demonstration platform.
  
  
• Denali Announces State-of-the-Art GHz DDR PHY Technology (Thursday Dec. 10, 2009)
  Denali today revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower.
  
  
• GDA Technologies Adds PowerPC(R) 440T90 Hard Macro to Its Portfolio Using TSMC 90nm Process Technology (Thursday Dec. 10, 2009)
  GDA Technologies has announced that it is adding IBM's PowerPC 440T90 to its existing 405S and 460S products using TSMC 90nm process technology.
  
  
• Mixel first to market with Unified MIPI/MDDI PHY IP solution (Wednesday Dec. 09, 2009)
  Mixel announced today the availability of the first MIPI/MDDI unified PHY IP solution. The IP combines a MIPI D-PHY compliant with revision 1.0 of the MIPI standard, with an MDDI-PHY compliant with revision 1.2 of the MDDI standard.
  
  
• IPextreme Teams Up with Infineon To Bring Complete Bluetooth IP Solution to Market (Wednesday Dec. 09, 2009)
  IPextreme has extended its partnership with Infineon Technologies AG to bring Infineon’s BlueMoon™ UniCellular Bluetooth® 2.1 solution featuring Enhanced Data Rate (EDR) functionality to the broad semiconductor market in the form of a complete licensable IP core.
  
  
• Xelic Announces Availability of 40G Enhanced Forward Error Correction Core for Optical Transport Networking Applications (Tuesday Dec. 08, 2009)
  Xelic today announced the expansion of their Enhanced Forward Error Correction core offering based on ITU-T G.975.1 Specifications.
  
  
• Sarnoff Releases Acadia II SoC Development Platform (Tuesday Dec. 08, 2009)
  Sarnoff Corporation, the leader in advanced embedded video processing, today introduced the Acadia® II Development Platform (A2-DP-1). The A2-DP-1 provides a complete engineering platform for evaluating and integrating the capability of the Acadia II SoC, along with customer developed algorithms and system level processing.
  
  
• CEVA Unveils Industry's First C-Based Application Optimization Toolchain for Licensable DSPs (Monday Dec. 07, 2009)
  CEVA-Toolbox™ Software Development Environment includes new Application Optimizer, significantly reducing software development time and improving performance of customers’ target applications by more than 60%
  
  
• ARM Cortex-M0 Processor - Fastest Licensing ARM Processor (Thursday Dec. 03, 2009)
  ARM announced today that the Cortex™-M0 processor is the fastest licensing ARM® processor, having secured 15 licenses already this year, with more predicted by the end of 2009. Cortex-M0 was released just nine months ago.
  
  
• Evatronix Usb-if verified USB 3.0 Device controller achieves over 430 mb/s (Thursday Dec. 03, 2009)
  Industry’s top throughput, xHCI host verification and availability as a single-chip FPGA solution add even more value to the state-of-the-art USB 3.0 peripheral controller.
  
  
• Evatronix Announces Formation Of The Technical Advisory Board (Thursday Dec. 03, 2009)
  Evatronix announced today the formation of the Technical Advisory Board and also the appointment of the TAB members. The members are Carl Das, Ph.D. - Director of ASIC Services at IMEC; Jean Mermet, Ph.D. - Chief Scientist of SAFEtronix; Prof. Dr. Wolfgang Rosenstiel - professor for Computer Engineering at the University of Tübingen, and Richard Tobias, Vice President of Operations and Engineering at Samplify Systems, Inc.
  
  
• Novocell Semiconductor Announces the Development Of A Multi-Time Programmable Antifuse Bit Cell (Wednesday Dec. 02, 2009)
  Novocell today announced the development of 2nTP, a new multi-time programmable (MTP) technology that allows the programming of its one-time programmable (OTP) antifuse bit cell up to eight (8) times. 2nTP can be configured as a two, four, or eight times write, and it is based on the NovoBlox™ bit cell, a non volatile memory (NVM) already proven at leading foundries.
  
  
• Sonics Offers Free Evaluation for Designers of Sonics Network for AMBA Protocol Solution (Tuesday Dec. 01, 2009)
  Sonicsannounced that its Sonics Network for AMBA® Protocol (SNAP™) will offer SoC designers, free-of-charge, tools and IP for capturing and analyzing bus designs with the release of its new Web-based SNAP evaluation environment
  
  
• Actel Extends Core8051s Processor Support to Rtax, Axcelerator and IGLOO Families (Monday Nov. 30, 2009)
  Continuing to deliver solutions for embedded designers, Actel Corporation (NASDAQ: ACTL) today announced that it has extended Core8051s support for its line of high-reliability Axcelerator®, radiation-tolerant RTAX and low-power IGLOO® FPGAs.
  
  
• MoSys Announces Availability of Silicon Proven 40nm DDR3 and DDR3/2 Combo PHYs with Support for Datarates up to 2133 Mbps (Monday Nov. 30, 2009)
  MoSys today announced the availability of its silicon-proven DDR3 and DDR3/2 combo PHYs. MoSys’ fully-integrated solution complies with the latest DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3/2 DRAM devices.
  
  
• Synopsys Expands DesignWare Data Converter IP Portfolio with 40-nm Solutions (Tuesday Nov. 24, 2009)
  Synopsys today announced the release of a broad range of data converter IP solutions for 40-nanometer (nm) process technologies. The IP is targeted at broadband wireless communications, wired communications, and video designs requiring high-performance, ultra-low power consumption and very compact area.
  
  
• Imagination Technologies' to deliver production-ready IP for POWERVR SGX543MP multi-processor graphics (Tuesday Nov. 24, 2009)
  Imagination Technologies will begin shipping fully verified production quality IP for its POWERVR SGX543MP multiprocessor graphics cores to partners before the end of December 2009.
  
  
• Imagination reveals new META family of embedded SoC processors (Tuesday Nov. 24, 2009)
  Imagination Technologies announces the full roadmap for its Series2 generation of META processors, designed for the SoC-centric (System-on-Chip) age of silicon design.
  
  
• Imagination Technologies introduces "Connected Processor" IP cores (Tuesday Nov. 24, 2009)
  Imagination Technologies has created a new class of embedded Connected Processor™ solutions that will power the ‘Internet Everywhere’ generation of consumer electronics.
  
  
• Evatronix Announces ONFi 2.2 High-Speed Interface Support to its NAND Flash Memory Controller (Monday Nov. 23, 2009)
  Evatronix today announced its NAND Flash memory controller has been updated to meet the latest specifications of the Open NAND Flash interface (ONFi) and now fully supports the newest High Speed NAND Flash.
  
  
• Arasan Chip Systems' Redesigned USB 2.0 Hub IP enables Compound Devices to share USB Port (Monday Nov. 23, 2009)
  Arasan announced today the increased adoption of its redesigned USB 2.0 Hub Controller IP core in building compound USB devices. Arasan Chip Systems is a pioneering provider of USB IP with over a hundred licensees of its USB IP cores.
  
  
• DMP adds OpenGL ES 2.0 shader-based graphics IP to its new "SMAPH" graphics IP core family (Monday Nov. 23, 2009)
  Digital Media Professionals today announced "SMAPH-S", a next generation OpenGL ES 2.0 shader-based graphics IP core. DMP will start providing the core to initial customers in 1Q 2010.