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IP / SOC Products News

• Virage Logic Introduces New Product for Post Silicon Bring Up and System Debug (Wednesday Nov. 18, 2009)
  Virage Logic today announced it has added a new member, STAR(TM) (self test and repair) Silicon Browser, to its flagship STAR(TM) Memory System product family.
  
  
• Imagination's POWERVR VXD390 adds key new functions to maximise system level performance (Wednesday Nov. 18, 2009)
  Imagination Technologies announces the latest member of its video decode IP core family, POWERVR VXD390: a low power, high performance, multi-standard and multi-stream high definition, hardware video decoder IP core that now also offers a broadcast quality video scaler, robust error and non-compliant stream handling capabilities, enhanced JPEG processing and optimisations for DDR3 memory support.
  
  
• Imagination Technologies announces revolutionary ENSIGMA UCCP320 (Wednesday Nov. 18, 2009)
  Imagination Technologies announces ENSIGMA UCCP320, which uniquely enables the broadest range of Wi-Fi connectivity, digital radio, mobile TV and TV standards of any communications and connectivity core.
  
  
• Imagination delivers latest HD video encoder IP core with full H.264 High Profile capability (Wednesday Nov. 18, 2009)
  Imagination Technologies announces POWERVR VXE380, the latest member of Imagination’s third generation video encoder IP family, which delivers multi-standard encoding of video, now including H.264 High Profile (HP), at HD resolutions.
  
  
• Rapid Bridge Tapes Out World's Smallest USB 2.0/3.0 PHY (Tuesday Nov. 17, 2009)
  Rapid Bridge announced today that it has taped out the world’s smallest USB 2.0/3.0 PHY. The USB 2.0/3.0 PHY is the newest member of Rapid Bridge’s LiquidPHY™ product family.
  
  
• Arasan Chip Systems First to Release SD/SDIO 3.0 Combo Device Controller IP (Monday Nov. 16, 2009)
  Arasan announced today the availability of the World's first Secure Digital SD/SDIO 3.0 Combo Device Controller IP. This combo IP is compliant with the latest SD, SDIO specification v3.0.
  
  
• Altera Delivers Industry's First Serial RapidIO 2.1 IP Solution (Monday Nov. 16, 2009)
  Altera today announced the immediate availability of the industry's first intellectual property (IP) core supporting the RapidIO® 2.1 specification. Altera's Serial RapidIO IP core supports up to four lanes at 5.0 GBaud per lane, addressing the increased bandwidth and reliability needs of the wireless and military markets.
  
  
• Actel Strengthens Fusion Mixed-Signal FPGA IP Offering for xTCA Platform Management Applications (Monday Nov. 16, 2009)
  Actel today announced IP core enhancements for hardware platform management applications. Developed in close collaboration with Pigeon Point Systems the new and improved cores further strengthen the suitability of Actel Fusion® mixed-signal FPGAs for platform management applications, and especially xTCA™ applications, for which Pigeon Point offers the market-dominant Board Management Reference (BMR) series.
  
  
• Tiempo demonstrates breakthrough performance for contactless secured applications, improving processing speed by a factor 6 (Monday Nov. 16, 2009)
  Tiempo is demonstrating at the “Cartes 2009” event how its asynchronous design technology can dramatically improve processing speed for contactless applications with, as an illustration, a live demo of a secured PayPass™ transaction in which processing speed on the card is six times faster than industry implementations, showing a complete transaction in less than 60 ms.
  
  
• Dolphin Integration complements its 130 nm catalog with a low voltage release of the ROM Cassiopeia (Friday Nov. 13, 2009)
  The patented Cassiopeia architecture for single via programmable ROM is enriched with a capability to operate from nominal voltage down to 1.1 V , both +/- 10%, in the TSMC 130 nm LP process.
  
  
• Posedge Annouces High Performance 10 Gbps IEEE 802.1AE (MACsec) IP Core (Thursday Nov. 12, 2009)
  Posedge has announced the availability of L2SEC Soft IP Core that performs full duplex 10 Gbps MAC layer Security fully conforming to IEEE 802.1AE standard.
  
  
• Arasan Chip Systems Releases ONFI 2.2 NAND Flash Controllers (Wednesday Nov. 11, 2009)
  Arasan announced the availability of NAND Flash Controllers supporting the newest Open NAND Flash Interface (ONFI) 2.2 specification.
  
  
• QualCore Logic successfully validated various Analog IP cores and Special IO's (Tuesday Nov. 10, 2009)
  QualCore Logic today announced that it successfully validated various Analog IP cores and Special IO's for US based company - the leading providers of high performance non-volatile solid state drives.
  
  
• Arteris Enhances Network-on-Chip Offerings to Address Full Range Of SoC Designs (Monday Nov. 09, 2009)
  Arteris today announced the availability of two new on-chip interconnect products, the FlexNoC and FlexWay packages. With these offerings, Arteris expands the capabilities of its market-leading NoC Solution to address the complete range of SoC design styles, sizes and complexities.
  
  
• Dolphin Integration launches a new breed of cache controller, dynamically self-configured to minimize power consumption (Friday Nov. 06, 2009)
  Traditional cache controllers are offered to improve the system frequency, involving a CPU and its program memory. But these caches are not concerned with power consumption. As a consequence, these solutions do not fit applications targeting low power. To bridge this gap, Dolphin Integration offers a new breed of cache controller: I-Stratus-LP.
  
  
• ASICS World Services Announces USB 3.0 Device IP Core (Tuesday Nov. 03, 2009)
  ASICS World Services, LTD. today released it's USB 3.0 Device IP Core. The USB 3.0 Device IP Core, supports SuperSpeed transfer speeds of 5Gbit/sec., and can be implemented in any technology, from FPGA to full custom ICs. Direct support is provided for Xilinx Virtex 5 FPGA with GTX transceiver, offering a true single chip solution, without the need for external PHYs. This IP Core also features an industry standard PIPE PHY interface for integration with 3rd party PHYs.
  
  
• HDL Design House Announces I2S Soft IP Core (Tuesday Nov. 03, 2009)
  HDL Design House has announced I2S soft IP core (HIP 3700). HIP 3700 I2S soft IP core is based on a generic, highly modular architecture from which a variety of solutions can be easily created to effectively and efficiently address customers’ specific requirements.
  
  
• Arasan Chip Systems Announces CompactFlash 4.1 Controller Family (Tuesday Nov. 03, 2009)
  Arasan announced the availability of CompactFlash/CF+ IP Host and Device cores that are compliant with CF+ and CompactFlash(R) Specification Revision 4.1.
  
  
• Noesis Technologies releases ITU G.704 E1 Framer/Deframer IP core (Tuesday Nov. 03, 2009)
  Noesis Technologies announced today the immediate availability of its ITU G.704 compliant E1 Framer/Deframer IP core (ntE1_G704).The IP core is designed for E1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.163.
  
  
• MIPS Technologies Introduces New Processor Cores with 32-bit Performance and near 16-bit Code Size (Monday Nov. 02, 2009)
  MIPS today introduced a new core family providing the highest levels of system performance for extremely cost-sensitive embedded applications such as 32-bit microcontrollers (MCUs), home entertainment, personal entertainment and home networking. The new MIPS32® M14K and M14Kc cores are the first MIPS32-compatible cores that also execute the new microMIPS instruction set architecture (ISA), achieving high performance of 1.5 DMIPS/MHz with an advanced level of code compression.
  
  
• MoSys Announces Availability of 40nm PCI Express 2.0 PHY (Monday Nov. 02, 2009)
  MoSys today announced the availability of its PCI Express 2.0 PHY. MoSys' PHY complies with the PIPE 2.0 specification and provides the physical layer (PHY) interface that connects to industry standard PCI Express 2.0 controllers.
  
  
• Dolphin Integration introduces Orion, the densest ROM (Monday Nov. 02, 2009)
  Orion is the latest ROM architecture conceived by Dolphin Integration. Benefiting from the “Two in one” Patent for high density, the metal-programmable ROM Orion enables SoC designers to get an impressive decrease of fabrication costs. The Orion architecture is already available for the TSMC 90 nm LP process.
  
  
• New Tensilica DPU Family Delivers 10 GigaMAC/sec DSP Performance, Tops 1 GHz Mark (Monday Nov. 02, 2009)
  Tensilica today introduced the Xtensa LX3 high-performance dataplane processor (DPU) core optimized for digital signal processing (DSP) and control in the system-on-chip (SOC) dataplane.
  
  
• Synopsys Unveils 30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm Processes (Thursday Oct. 29, 2009)
  Connectivity IP Leader Continues to Innovate with the DesignWare USB 2.0 picoPHY - The First PHY IP to Support USB 2.0 Battery Charging v1.1 and OTG 2.0 Specifications
  
  
• Sital Announces the release of Mil-Std-1553 IP core with PCI interface (Wednesday Oct. 28, 2009)
  Sital Technology is expanding its IP products base with the release of the new Mil-Std-1553 IP Core with the addition of PCI interface.
  
  
• Synopsys Announces 40th DesignWare Audio Codec IP (Wednesday Oct. 28, 2009)
  Synopsys today announced the availability of its 40th audio codec IP with the release of the DesignWare 96 dB Hi-Fi Audio IP in the SMIC 65-nanometer (nm) process.
  
  
• Arasan Chip Systems First to Announce SDIO 3.0 Device Controller IP (Tuesday Oct. 27, 2009)
  Arasan announced today the availability of the world's first Secure Digital IO (SDIO) 3.0 Device Controller IP compliant with the latest SDIO Specification v3.0.
  
  
• Dolphin Integration launches Linear Regulators at 65 nm for Ultra Low-Noise (Monday Oct. 26, 2009)
  Dolphin Integration continues its strategy with Inductorless converters and announces today the availability of its latest Low Drop Out Linear Regulator at 65 nm.
  
  
• Jointwave Announces Green H.264 HD Encoder IP (Monday Oct. 26, 2009)
  Jointwave announces its new E2, E3, and E3 series of H.264 HD Video Encoder ASIC IP, which targets super low power consumption products for mobile and embedded applications.
  
  
• Rambus Achieves Power Efficiency Breakthrough for Mobile Memory Solutions (Wednesday Oct. 21, 2009)
  Rambus today announced it has achieved a new breakthrough level of power efficiency with its latest silicon test vehicle developed through its Mobile Memory Initiative (MMI). The latest silicon-validated results demonstrate that through the use of MMI innovations, a high-bandwidth mobile memory controller can achieve a world-leading power efficiency of 2.2mW/Gbps.