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IP / SOC Products News

• ARM Unveils New AMBA System IP For Low Power and Media Rich SoC Designs (Wednesday Oct. 21, 2009)
  ARM today announced the launch of new system IP products from the ARM® AMBA® family: the AMBA Network Interconnect with Advanced Quality of Service, a new Dynamic Memory Controller, and the Verification and Performance Exploration tool.
  
  
• ARM Delivers The Internet Everywhere With Most Power-Efficient and Cost-Effective Multicore Processor (Wednesday Oct. 21, 2009)
  ARM today announces the launch of the ARM® Cortex™-A5 MPCore™ processor, the smallest, lowest power ARM multicore processor capable of delivering the Internet to the widest possible range of devices, from ultra low cost handsets, feature phones and smart mobile devices, to pervasive embedded, consumer and industrial devices.
  
  
• Tensilica Introduces Small, Ultra-Low Power Dataplane Processor Core for Deeply Embedded Control (Monday Oct. 19, 2009)
  Tensilica today introduced the Xtensa 8 customizable processor, the eighth generation of its market leading low-power dataplane processor cores (DPUs). The Xtensa 8 processor core starts at a size of just 15,000 gates, consuming less than 0.05mm2 in 40nm process technology - making it one of the smallest licensable controller cores on the market.
  
  
• Jointwave presents H.264 solution for FPGA/ASIC (Monday Oct. 19, 2009)
  Jointwave LLC, a leading provider of video codec IP, presented its H.264 series encoder in HYSTA 2009 Annual Conference
  
  
• Arasan First to release SD3.0 Family of Host Controller IPs (Thursday Oct. 15, 2009)
  Arasan formally announced today the availability of the world's first, proven, Secure Digital eXtended Capacity (SDXC) / SDIO 3.0 / eMMC 4.4 Host Controller IP. This IP is compliant with the latest SD Physical Layer Specification v3.0, Part E1 SDIO 3.0 specification and JEDEC's eMMC 4.4 specification. SoC designers now have the flexibility to tailor their memory subsystem to the functional requirements of their platforms.
  
  
• Tensilica's HiFi Audio DSP First IP Core to Achieve DTS-HD Master Audio Logo Certification (Tuesday Oct. 13, 2009)
  Tensilica, Inc. announced today that it has been granted DTS-HD Master Audio logo certification for the HiFi Audio DSP (digital signal processor). This makes Tensilica's HiFi Audio DSP the first IP (intellectual property) core to achieve certification.
  
  
• Silicon Image Introduces New 18 Megapixel Camera Processor IP Core (Monday Oct. 12, 2009)
  Silicon Image today introduced the camerIC-18, the newest member of its family of camerIC camera processor IP cores. With its high-quality 18 megapixel (MP) image signal processing (ISP) technology, the camerIC-18 is targeted for integration into digital still camera (DSC) and video System-on-a-Chip (SoC) application processors for mobile devices such as cell phones, portable multimedia players (PMPs) and netbooks.
  
  
• Xelic Announces Availability of Two New Cores in support of ITU G.Sup43 for Optical Transport Network (OTN) Applications (Monday Oct. 12, 2009)
  Xelic today announced the availability of their new 10G Multiprotocol Mapper Core (XCO2M) along with a PCS to XGMII Encoder/Decoder Core (XCI2PX) for OTN applications. These two cores are the latest in Xelic's growing portfolio of cores for OTN Applications.
  
  
• On2 Technologies Releases Hantro 9190 Multiformat Hardware Decoder with On2 VP6 Support (Thursday Oct. 08, 2009)
  On2 today announced that it has released its new flagship hardware video decoder design, the Hantro(TM) 9190. The 9190 design supports video playback up to full HD (1080p) resolution at 60 frames per second (fps) in multiple formats including On2 VP6 for Adobe Flash Player and Sun JavaFX, DivX 3, 4, 5, 6, H.264, H.263, Sorenson Spark, MPEG-1, MPEG-2, MPEG-4, VC-1/WMV9 and RealVideo 8, 9 & 10, as well as up to 66 megapixel JPEG still images.
  
  
• ARM Announces 45nm SOI Test Chip Results That Demonstrate Potential 40 Percent Power Savings Over Bulk Process (Thursday Oct. 08, 2009)
  ARM announced the results from a silicon-on-insulator (SOI) 45nm test chip that demonstrate potential power savings of up to 40 percent over traditional bulk process for manufacturing chips. The test chip was based on an ARM 1176™ processor and enables a direct comparison between SOI and bulk microprocessor implementations.
  
  
• IMEC's multi-threaded ADRES processor architecture ready for licensing (Tuesday Oct. 06, 2009)
  Today, IMEC unveils the second generation of its ADRES processor architecture (architecture for dynamically reconfigurable embedded systems). ADRES now supports multithreading, and has doubled its performance and energy efficiency compared to the first ADRES generation. This positions ADRES as a building block for future 4G devices. ADRES can be licensed from IMEC and is targeted at chip manufacturers.
  
  
• Dolphin Integration paves the way to the "Super-ViC" generation for audio applications (Friday Oct. 02, 2009)
  Dolphin Integration today is paving the way to a new generation of Virtual Components starting with loDAC95-SV01, the first audio DAC empowered with its own oscillator and embedded voltage regulator.
  
  
• Arasan Chip Systems First to Release MIPI D-PHY Compliant with the version 1.0 Specification (Wednesday Sep. 30, 2009)
  Arasan announced the availability of the MIPI® D-PHY IP compliant with the v1.0 standard released September 22, 2009 by the MIPI Alliance. With this release, Arasan continues to demonstrate its commitment to its Strategic Mobile Initiative by being the first to deliver fully verified MIPI IP comprising of software stacks, controllers and the D-PHY.
  
  
• Moortec Announces SPI Block (MR74040) for Low Power Applications (Tuesday Sep. 29, 2009)
  Moortec Announces SPI Block (MR74040) for Low Power Applications. The MR74040 is a synchronous serial-data interface adhering to the SPI protocol of communications.
  
  
• Virage Logic Expands SiPro(TM) Product Portfolio with New Production-Proven Advanced Interface IP Offerings (Tuesday Sep. 29, 2009)
  Virage today announced new additions to its recently introduced SiPro(TM) product line of production-proven advanced interface IP. The expanded product line now includes complete standards-based solutions for PCI Express (PCIe) and Mobile Industry Processor Interface (MIPI(R)) as well as a unique multi-protocol IP solution for High-Definition Multimedia Interface (HDMI), Digital Visual Interface (DVI) and DisplayPort interfaces. The Virage Logic SiPro product portfolio is the result of a collaboration with AMD (NYSE: AMD) that was announced in January 2009.
  
  
• Evatronix Introduces the World's Fastest SD/SDIO/MMC Host Controller (Wednesday Sep. 23, 2009)
  Evatronix today announced its SDIO-HOST controller has been updated to meet the latest specifications and now supports SD 3.0, SDIO 2.0 and MMC/eMMC 4.4 standards. These specifications allow support of SDXC cards, which go beyond the 32 GB limit of SDHC products and sets the capacity bar at 2 TB of data.
  
  
• eMemory Breaks New Ground in Launching Its Industrial Grade Embedded NVM for Power Management Solution (Wednesday Sep. 23, 2009)
  eMemory today announces its Neobit OTP memory has reached higher temperature stability up to maximum 125℃ for minimum 10 years data retention (125℃/10yrs). The 125℃/10yrs Neobit is the first logic OTP memory solution that has passed 0.35um BCD process qualification and entered into commerce in volume production in TSMC.
  
  
• Dolphin Integration Library portfolio at 65 nm (Monday Sep. 21, 2009)
  Dolphin Integration focuses on providing users with a full offering featuring embedded memories and standard cells of diverse optimizations for the 65 nm process node.
  
  
• Rambus and Kingston Co-Develop Threaded Module Prototype for Multi-Core Computing (Thursday Sep. 17, 2009)
  Rambus and Kingston Technology today announced a collaborative development of a threaded module prototype using DDR3 DRAM technology. Initial silicon results show an improvement in data throughput of up to 50 percent, while reducing power consumption by 20 percent compared to conventional modules.
  
  
• Faraday SATA 3G PHY & controller First to Achieve Compliance in UMC's 90nm Process Technology (Thursday Sep. 17, 2009)
  Faraday Technology today announced that their SATA 3G solution is the first to pass SATA-IO compliance test in UMC's 90 nanometer process technology, and becomes the 2nd IP provider in the world to have IP in SATA-IO's Building Block Listing.
  
  
• Cycleo unveils its first innovative semiconductor IP bringing unprecedented range to wireless data transmission (Thursday Sep. 17, 2009)
  Cycleo today announces Lora™, an innovative semiconductor IP bringing unprecedented range to wireless data transmission. Based upon a disruptive patented technology, Lora (as Long Range) allows robust long range wireless communications at very low power.
  
  
• ARM Announces 2GHz Capable Cortex-A9 Dual Core Processor Implementation (Wednesday Sep. 16, 2009)
  ARM announced today the development of two Cortex™-A9 MPCore™ hard macro implementations for the TSMC 40nm-G process, enabling silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz.
  
  
• Arasan Chip Systems adds IEEE 1588 PTP support to Ethernet IP Core (Wednesday Sep. 16, 2009)
  Arasan announced that it has expanded its Ethernet Portfolio by integrating hardware support for IEEE 1588 Precision Time Protocol (PTP). Mission critical environments such as factory automation systems, networking environments, manufacturing, test and measurement systems rely on IEEE 1588 to maintain precise timing synchronization in order to execute activities in real-time.
  
  
• Microtronix Boosts Performance of MDDR Memory Controller IP Core to 200 MHz (Wednesday Sep. 16, 2009)
  Microtronix today announced an upgrade of their Multi-port MDDR Memory Controller IP Core to support 200 MHz Mobile DDR (MDDR) memory devices. This upgrade represents an approximate 20% boost in system performance from the previous version.
  
  
• Element CXI Announces nGEN Elemental Computing Array, a Fully Reconfigurable Platform for 4G Networks (Monday Sep. 14, 2009)
  Element CXI today introduced its new nGEN Elemental Computing Array (ECA) platform at 4G World in Chicago. The nGEN ECA offers OEMs a common platform for end-to-end, software defined solutions from baseband to front-end processing.
  
  
• Radiocomp releases 4G Ready OBSAI RP3 v4.1 IP core for LTE, WCDMA and WIMAX (Wednesday Sep. 09, 2009)
  Radiocomp's OBSAI RP3 v4.1 IP core comes ready with a fully-flexible and multi-standard IQ mapping module with embedded Ethernet MAC functionality, thereby minimizing engineering efforts and time to market for standards-based radio access products for LTE, GSM, WCDMA, CDMA and WIMAX.
  
  
• Synopsys First to Announce DDR3 IP with Support for 2133 Mbps Data Rates and 1.35V DDR3L (Wednesday Sep. 09, 2009)
  Synopsys today announced that its DesignWare® DDR3/2 PHY and digital controller IP supports the emerging 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard.
  
  
• Barco delivers its JPEG 2000 IP cores on all 40nm FPGA platforms (Monday Sep. 07, 2009)
  Barco Silex, Barco's center of competence for embedded video coding electronic and design services, announces the support of its JPEG 2000 IP cores on all high-performance and low-cost 40nm FPGA families.
  
  
• SiliconGate Introduces 50 nA Crystal Oscillator for 0.35um to 40-nm Process Technologies (Wednesday Sep. 02, 2009)
  SiliconGate's Nano Power Crystal Oscillators are fully integrated and require no external capacitors or references. The IP is made available in leading process technologies from 0.35-μm down to 40-nm, and includes behavioral models for system development.
  
  
• Altera's RapidIO IP Core Passes RIOLAB Device Interoperability Testing (Tuesday Sep. 01, 2009)
  Altera today announced its RapidIO® MegaCore function, version 9.0, successfully passed RIOLAB's Device Interoperability Level-3 (DIL-3) testing. Altera is the first FPGA vendor to offer a Serial RapidIO intellectual property (IP) core that is fully qualified by RIOLAB.