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IP / SOC Products News

• Dolphin Integration announces a benchmarking solution for fair comparison of the in-SoC performances of embedded memories (Monday Aug. 31, 2009)
  With the objective to avoid any illusion about density, Dolphin Integration proposes a virtual component of IP, named LOGOS, as an alternative to the traditional memory evaluation process based on compiler outputs.
  
  
• iWave announces the Host controller for SDXC card which is compatible with the SD Physical Layer specification V3.0 (Monday Aug. 31, 2009)
  iWave announces the Host controller for SDXC which is compatible with the SD Physical Layer specification V3.0.The core developed, supports 32 bit AHB LITE Host interface working at SOC interface frequency and is compatible with the standard register set for the host controller as per SD host controller specification Version2.0.
  
  
• Arasan Chip Systems adds MIPI HSI IP to its Strategic Mobile Initiative Program (Wednesday Aug. 26, 2009)
  Arasan announced the release of its MIPI® High Speed Synchronous Interface (HSI) Controller IP and Software Stack. The HSI Controller IP and Software Stack are compliant with the HSI v1.0 specification.
  
  
• Rapid Bridge Introduces LiquidCell Library to Bring Unparalleled Flexibility to Chip Design at 40 Nanometer Process Node (Wednesday Aug. 26, 2009)
  Rapid Bridge announced today that its revolutionary LiquidCell™ library is now available at 40nm process node. LiquidCell consists of a metal-programmable sea of transistors that can be configured into millions of usable elements from a library of over 700 standard cells.
  
  
• Tensilica's ConnX D2 DSP Engine Combines Outstanding Performance, Compact Size, and Easy Programmability (Monday Aug. 24, 2009)
  Tensilica today introduced the high-performance, small, low-power ConnX D2 16-bit dual-MAC (Multiply Accumulator) DSP (Digital Signal Processor) engine for its proven Xtensa LX dataplane processor cores for SOC (System-on-Chip) designs. The ConnX D2 DSP engine provides uncompromised performance from C code, unlike many other DSPs that require time consuming assembly coding for maximum performance.
  
  
• intoPIX introduces optimized Spartan-6/Virtex-6 JPEG 2000 encoders & decoders range focusing on Low Power and Ultra High Resolution (Monday Aug. 24, 2009)
  intoPIX announces the company’s migrating solution for Xilinx® Spartan-6 & Virtex-6 FPGA platforms. With this release, intoPIX enables its customers with a new range of JPEG 2000 IP-Cores, allowing them to significantly reduce their Bill of Materials while giving access to higher performances.
  
  
• Elliptic Curve CryptoProcessor Core from Athena Set New Standard for NIST P-Curve Performance (Wednesday Aug. 19, 2009)
  The Athena Group today announced the industry's fastest elliptic curve accelerator core. With an incredibly small area footprint, starting at less than 200K-gates, the E5200 is both the highest performance core available and the highest density in terms of performance per unit area.
  
  
• Arasan Chip Systems Announces SDXC Card Controller IP (Wednesday Aug. 19, 2009)
  Arasan announced today the availability of the World’s first Secure Digital eXtended Capacity (SDXC) Card Controller IP compliant with the latest SD Memory Specification v3.0. Arasan’s SDXC Card Controller supports Ultra-High Speed I (UHS-I) operation and incorporates all standard security features.
  
  
• Faraday Offers 55nm/ 65nm miniIO with around 40% Area-Saving and Robust ESD Performance (Tuesday Aug. 18, 2009)
  Faraday Technology Corporation (TAIEX: 3035) today announced the availability of its innovative miniIO™ at 55nm and 65nm. Compared with general IO pads, Faraday's miniIO™ reduces the chip area by up to 40% for a pad-limited design with 500 pins, while keeping the same programming IO functionality, and achieving robust ESD performance.
  
  
• Synopsys Delivers Comprehensive HDMI IP Solution for 90-nm to 40-nm Process Technologies (Thursday Aug. 13, 2009)
  Synopsys' DesignWare® IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability anticipated at the end of 2009.
  
  
• Micron Validates Denali's NAND Controllers for High-Performance Applications (Monday Aug. 10, 2009)
  Denali today announced that Micron Technology has validated Denali's Databahn NAND Flash controller IP and FlashPoint products with its line of ONFI 2-based flash devices.
  
  
• Evatronix Fastest 8051 Microcontroller Now Fully Supported by ARM Keil uVision4 IDE (Monday Aug. 10, 2009)
  Evatronix SA, today announced the full support of its R8051XC2 microcontroller IP, the world’s fastest 8051 compatible design, by the ARM® Keil™ μVision4 Integrated Development Environment.
  
  
• Perceptia confirms performance of 11-GHz 0.4-ps 40-nm DSP-based PLL hard IP Core (Thursday Aug. 06, 2009)
  Perceptia today confirmed functionality and ultra-high performance of its DeepSub™ pPLL01 hard IP core. The pPLL01 has an output frequency ranges from 9 to 11-GHz and can be driven from sources down to 20-MHz.
  
  
• Altera Releases CPRI v4.1 IP Core for Wireless Basestation and Remote Radio Head Design (Monday Aug. 03, 2009)
  Supporting channel speeds up to 6.144 Gbps, the CPRI v4.1 IP core supports the LTE and WiMAX standards and offers legacy support for WCDMA, CDMA and other air-interface standards in a single system.
  
  
• Crack Semiconductor Introduces The CS1024-RSA Light-Weight RSA Offload Processor (Monday Aug. 03, 2009)
  Crack Semiconductor introduces the CS1024-RSA, an RSA-only variant of its CS1024 PKA Processor with the SIMPLR(tm) integer state aware data path and "on-the-fly" reconfigurable ALU controller for a very high performance to gate area ratio.
  
  
• HDL Design House announces Serial Rapid IO soft IP core (HIP 3300) (Friday Jul. 31, 2009)
  HDL Design House has announced Serial RapidIO soft IP core (HIP 3300) compliant with RapidIO specification version 2.0.1 . HIP 3300 Serial RapidIO endpoint soft IP core is based on a generic, highly modular architecture from which a variety of solutions can be easily created to effectively and efficiently address customers’ specific requirements.
  
  
• Arasan Chip Systems First to Announce e.MMC 4.4 Card Controller IP Core (Wednesday Jul. 29, 2009)
  Arasan announced the availability of the Embedded MultiMedia 4.4 Card Controller IP compliant with the recently ratified JEDEC e·MMC 4.4 standard. Arasan’s e·MMC 4.4 Card Controller enables memory card designers to support the higher bandwidth and new security, card partition features offered by e·MMC 4.4.
  
  
• Virage Logic Introduces Volume Production-Proven SiPro PCI Express PHY IP (Tuesday Jul. 28, 2009)
  Virage Logic today announced its new offering, a silicon and volume production-proven 40-nanometer (nm) G PCI Express Gen1/Gen2 Physical Layer (PHY). The SiPro™ PCI Express PHY product line represents the first offering in Virage Logic’s advanced interface IP SiPro product portfolio that is a result of its collaboration with AMD announced in January 2009.
  
  
• Virage Logic Extends IP Technology Leadership to the 32/28nm Process (Tuesday Jul. 28, 2009)
  Virage Logic today announced it has extended its advanced IP technology leadership to the 32/28-nanometer process node with the tape out of a product test chip with multiple IPs optimized for a high performance application for an early adopter customer.
  
  
• Dolphin Integration launches moDAC95-LB combining smallest silicon area and optimized Bill-of-Material (Monday Jul. 27, 2009)
  In the move to approach systematically the key segments of high-resolution audio converters, Dolphin Integration launches moDAC95-LB - which stands for Low Bill-of-material - a Digital Audio Converter targeting "nomad consumer devices" with a SNR as high as 95 dB.
  
  
• ARM Announces Ultra Low-Power Physical IP Technology to Drive Next-Generation MCU Devices (Monday Jul. 27, 2009)
  The ARM® 0.18µm ultra low power libraries (uLL), coupled with the inherent power management advantages of the ARM Cortex™ processor family and the TSMC 0.18µm embedded flash uLL/HDR “high data retention” process provides SoC designers with additional reduction in power leakage up to 10x compared to 0.18um G implementations.
  
  
• Evatronix Releases JPEG 2000 Image Compression Encoder Optimized for FPGA Designs (Monday Jul. 27, 2009)
  Evatronix SA, announced today the availability of the JPEG 2000 Encoder IP core. The encoder has been optimized for FPGA designs and takes a minimum number of slices while providing full compatibility with ISO/IEC 15444-1 standard that defines the JPEG 2000 format.
  
  
• Kilopass Lowers Manufacturing Cost With ROM Conversion Option (Monday Jul. 27, 2009)
  Kilopass Technology announced today that it is providing a read only memory (ROM) conversion option for its One-Time Programmable Memory (OTP) product lines. ROM-it! will eliminate programming test cost for OTP.
  
  
• Nangate Releases a New Version of the 45nm Open Cell Library (Thursday Jul. 23, 2009)
  Nangate has just released the fourth version of its open source 45nm standard-cell library. Along with the library, Nangate releases a freely distributed tool for creating HTML databooks from Liberty files, the Nangate Liberty Viewer™.
  
  
• Evatronix And Soft-Mixed Signal Announce USB 2.0 Total Solution (Thursday Jul. 23, 2009)
  Evatronix SA and Soft Mixed Signal announced today the availability of the complete USB 2.0 solution that integrates USB 2.0 Controller IP from Evatronix and the USB 2.0 PHY IP from Soft Mixed Signal.
  
  
• MOSAID Now Sampling HLNAND Flash Memory Semiconductor Chip and Module (Wednesday Jul. 22, 2009)
  MOSAID today announced that HLNAND™ (HyperLink NAND), the Company's breakthrough Flash memory architecture and interface, is now available for sampling. The devices are a 64Gb MLC (Multi Level Cell) HLNAND MCP (Multi-Chip Package), and a 64GB HLDIMM (HyperLink Dual In-Line Memory Module).
  
  
• Silicon Image Introduces New IP Core Product Family Supporting HDMI(R) 1.4 Features (Wednesday Jul. 22, 2009)
  Silicon Image today announced that it is expanding its market-leading family of HDMI(R) semiconductor intellectual property (IP) cores to include transmitter and receiver IP cores that incorporate features of the recently announced HDMI Specification Version 1.4.
  
  
• Virage Logic Offers Broadest Portfolio of Embedded Non-Volatile Memory (NVM) Solutions at TSMC (Tuesday Jul. 21, 2009)
  Virage Logic today announced it offers the broadest portfolio of embedded non-volatile memory (NVM) at TSMC, with fully qualified IP solutions ranging from 250nm down to 65nm. With a comprehensive selection of multi-time programmable (MTP) and few-time programmable (FTP) NVM IP, the AEON(R) product family addresses the needs of wireless, automotive, analog, power management and security applications.
  
  
• Chips&Media Delivers the Latest Full HD Codec IP Core Coda8550 (Tuesday Jul. 21, 2009)
  Chips&Media today announced that its new High definition multi-standard video IP core Coda8550. Coda8550, the first IP of the next generation of Chips&Media’s advanced Coda8 series, delivers full HD(1080p) encoding capability at 30fps under 200MHz clock frequency.
  
  
• Synopsys' New DesignWare IP Slashes Power in Datapath Circuits (Monday Jul. 20, 2009)
  Synopsys today announced the DesignWare® minPower Components, a new IP product that is an integral part of the Synopsys Eclypse™ Low Power Solution. By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic.