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IP / SOC Products News

• Synopsys Accelerates Development of System-On-Chip Designs With Complete IP Solution for PCI Express 3.0 (Wednesday Jul. 15, 2009)
  Synopsys today announced its complete DesignWare® IP solution for PCI Express® (PCIe®) 3.0 consisting of digital controllers, PHY and verification IP. Synopsys' DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for high-performance enterprise computing applications.
  
  
• Syntill8 to offer Mentor Graphics' M8051 Microcontroller IP and Support Services (Wednesday Jul. 15, 2009)
  Syntill8 today announced a reseller agreement with Mentor Graphics. Under the agreement Syntill8 will sell and support Mentor’s industry proven 8-bit microcontroller Intellectual Property (IP) cores. Syntill8’s CTO is the original designer of the majority of Mentor’s M8051 IP products.
  
  
• CAST Releases H.264 IP Core for Highest Quality HD Video Compression (Tuesday Jul. 14, 2009)
  CAST today announced the immediate availability of a new H.264 encoder core that delivers some of the best looking compressed video available. The core fully supports the Baseline Profile, Level 4.1, of the H.264 specification (MPEG-4 Part 10, also known as MPEG-4 AVC, Advanced Video Coding).
  
  
• Faraday Launches Its Low-leakage Memory with Up to 90% Leakage-reduction (Tuesday Jul. 14, 2009)
  Faraday today announced the availability of low leakage memory at UMC 90nm process, which provides up to 90% leakage reduction with no area penalty. Faraday's low leakage memory has been silicon proven via complete function verifications, targeting fabless design houses, foundries, system vendors and IDMs.
  
  
• Sital releases a PCI Interface IP core for the Aerospace market sector (Thursday Jul. 09, 2009)
  Sital releases a PCI Interface IP core for the Aerospace market sector. This PCI IP core was developed in order to overcome problems related to existing IP cores, specifically in the aerospace industry, where high reliability, wide temperature range and easy integration are key.
  
  
• Sarnoff Europe Becomes Sofics, Announces New System-Level ESD Solutions for High-Voltage ICs (Tuesday Jul. 07, 2009)
  Sarnoff Europe today announced that it is changing its corporate name to Sofics, and is introducing a new line of design solutions for high-voltage ICs that provide on-chip protection against damage from system-level electrostatic discharge (ESD).
  
  
• Dolphin Integration launches the BTF upgrade of its standard cell offering SESAME for 130 nm (Monday Jul. 06, 2009)
  Dolphin Integration continues their steady enhancement of the proprietary RCSL (Reduced Cell Stem Library) with the High Density stem HD-BTF for TSMC 130 nm G processes. Highly Dense and endowed with “Back-Tracking Freedom”, HD-BTF incorporates the latest architectural innovations from Dolphin Integration replacing classical flip-flops with their “spinner cell”.
  
  
• TSMC Unveils First Commercial 65-Nanometer Multi-Time Programmable Non-Volatile Memory Technology (Thursday Jul. 02, 2009)
  TSMC today announced the foundry segment’s first functional 65-nanometer (nm) multi-time programmable (MTP) non-volatile memory (NVM) process technology. The technology incorporates process-qualified MTP IP blocks jointly developed with Virage Logic.
  
  
• Cosmic Circuits tapes out 40nm Mixed Signal Test Chip (Wednesday Jul. 01, 2009)
  Cosmic Circuits announced the tape out of its TSMC 40nm Mixed Signal test chip. The test chip consists of several data converters and power regulators for Wireless Communications and Portable consumer applications.
  
  
• FFT Library from OptNgn Validated for use in Mentor Graphics' Precision FPGA Synthesis (Tuesday Jun. 30, 2009)
  OptNgn today announced that it has validated its newly released FFT WFTA Kernels Library of streaming IP cores for use with Mentor Graphics Precision® RTL Synthesis. These Winograd Fourier Transform (WFTA) kernels, along with their derivative 1D and 2D libraries, represent a vendor independent and high throughput way to use the cache-free FFT power available in FPGA coprocessors
  
  
• Dolphin Integration's Audio converter Helium lightens both Power consumption and Bill-of-Material (Tuesday Jun. 30, 2009)
  Low power consumption has become a hot selling argument for SoCs targeting nomad audio applications. Class D amplifiers have demonstrated their superior power efficiency for driving loud-speakers.
  
  
• Rambus Demonstrates Superior Power Efficiency of World's Fastest Memory (Tuesday Jun. 23, 2009)
  Rambus today showcased a silicon demonstration of a complete XDR™ memory system running at data rates up to 7.2Gbps with superior power efficiency.
  
  
• Sonics Combines DRAM Scheduler with Synopsys Protocol Controller For Integrated High-Performance Memory Subsystem (Tuesday Jun. 23, 2009)
  Sonics has announced the MemMax® DRAM System, a pre-configured, verified and silicon-proven IP block that can be integrated into a variety of SoCs quickly and easily. The IP block is a combination of Sonics’ advanced memory scheduler and Synopsys’ DesignWare® DDR Protocol Controller IP.
  
  
• Virage Logic's AEON(R) Becomes the First Multi-Time Programmable Embedded Non-Volatile Memory Available on a Standard CMOS Process Qualified to Rigorous Automotive Standard AEC-Q100 (Tuesday Jun. 23, 2009)
  Virage Logic today announced its AEON(R) multi-time programmable (MTP) non-volatile memory (NVM) solution is the first qualified to the stringent quality and reliability standards of the automotive industry using only standard CMOS processing.Automotive integrated circuits (ICs) demand reliability and qualification testing above and beyond the requirements of typical consumer or industrial applications.
  
  
• Dolphin Integration puts in the public domain a unique freeware for evaluation of Standard Cell libraries (Monday Jun. 22, 2009)
  Dolphin Integration announces the release of Motu Uta, a flexible logic circuit designed for being representative of complex logic designs. With Motu Uta, the company expects to speed-up the introduction of its innovative libraries of standard-cells and to help its potential users to reach in the shortest lead-time a conclusion on the benefit of its library stems versus contenders.
  
  
• Tensilica Announces High-Performance ConnX Baseband Engine for LTE and 4G Wireless DSP Handsets and Base Stations (Monday Jun. 22, 2009)
  Tensilica today announced the first member of its new ConnX family of digital signal processor (DSP) cores for system-on-chip (SOC) design. The ConnX Baseband Engine enables efficient baseband processing for 3G, LTE (Long-Term Evolution) and 4G wireless equipment with its scalable, high-performance DSP architecture that provides industry leading computational throughput of 16 18-bit MACs per cycle.
  
  
• VinChip Announces India's First Homegrown 32-Bit RISC Processor (Friday Jun. 19, 2009)
  VinChip Systems announces the immediate availability of its convergent 32-bit RISC processor, VinRZ5110. Its DSP enhanced instruction set architecture, low power design and optimized gate count makes it well suited for DSP and other embedded applications.
  
  
• ARM Mali GPUs Achieve Industry-Firsts With Khronos OpenGL ES 2.0 Conformance For 1080p and Multicore (Tuesday Jun. 16, 2009)
  ARM® Mali™ graphics processing units (GPUs) demonstrate technology leadership in graphics acceleration through conformance to the Khronos OpenGL ES 2.0 API with two industry milestones.
  
  
• Innovative Logic announces fully integrated USB3.0 Controller with PCS layer (Tuesday Jun. 16, 2009)
  Innovative Logic announced today the second release of USB 3.0 Device Controller IP. Inno-Logic’s USB3.0 IP offering includes implementation IP as well as verification IP by making use of industry standard latest tools and methodologies.
  
  
• Noesis Technologies Releases Fully Configurable Interleaver-Deinterleaver IP (Friday Jun. 12, 2009)
  Noesis Technologies announced today the availability of its new version of a fully configurable Interleaver-Deinterleaver IP core. The ntINT_DEINT is a fully configurable interleaver-deinterleaver compliant to a variety of industry standards such as DVB, ATSC, IEEE 802.16 e.t.c.
  
  
• Gennum's Snowbush IP Group Delivers the Industry's First PCI Expess 3.0 PHY IP on TSMC 40nm Process (Monday Jun. 08, 2009)
  Gennum today announced that its Snowbush IP group has developed the industry’s first available integrated PCI Express® 3.0 (Gen 3) PHY and Controller IP solution. The new PCIe® 3.0 cores can be licensed immediately by system-on-a-chip (SoC) and system companies, enabling early deployment of PCIe 3.0 (Gen 3) in systems requiring the 8.0 Gigatransfers per second (GT/s) performance of this new PCI-SIG standard. PCIe 3.0 opens up more bandwidth using the same physical connectors and adds new features to improve the user experience in server network and computer products using PCI Express.
  
  
• CAST Expands Video IP Cores Line with New Video Deinterlacer (Thursday Jun. 04, 2009)
  The new core converts incoming interlaced video to progressive video format for further processing or display. It accepts an industry- standard 8-bit ITU-R BT.656 video stream for wide compatibility, and its lean processing means it requires little ASIC or FPGA area and causes practically no video transmission delay.
  
  
• Synopsys Announces First DDR3 IP Verified in Silicon at 1600 Megabits per Second (Wednesday Jun. 03, 2009)
  Synopsys today announced that its DesignWare® DDR3/2 PHY and digital controller IP is the first DDR3 IP that has been fully verified in test silicon at 1600 Megabits per second (Mbps), the maximum data-rate of the JEDEC DDR3 specification.
  
  
• Palmchip Stimulates Economic Recovery by Offering Free Semiconductor IP Cores (Tuesday Jun. 02, 2009)
  Palmchip today announced the launch of their “SoCStart” IP Program providing free semiconductor IP cores. The company is also announcing the AcurX-51™, a SoC platform with integrated 8051 core. Designers can use this SoC platform to quickly start their SoC chip project. AcurX-51 is ported into Xilinx FPGA for rapid firmware and software development.
  
  
• Socle Partners with Catena, CoreSonic to Drive Wireless SoC Platform in 65nm as Mobile Solution (Monday Jun. 01, 2009)
  Socle Technology today announced its partnership with Catena and CoreSonic to develop a comprehensive design platform on Chartered’s 65nm process with integrateable wireless subsystems. Socle contributes its integrated and silicon-proven ARM9 and ARM11 design platforms. Catena provides its wireless subsystems for WiFi, WiMAX, and GPS functions, and CoreSonic offers its proven Wifi/WiMax baseband IP.
  
  
• C80186EC IP Core Added to the Evatronix 80186 Replacements Family (Monday Jun. 01, 2009)
  Evatronix announced today the release of the 80186EC IP core – a 16-bit microprocessor compatible with the 80c186ec chip from Intel®. The core implements a wide set of peripherals to address a variety of possible applications.
  
  
• Radiocomp releases their CPRI v4.0 compliant IP core for LTE, WCDMA, CDMA and WIMAX supporting speeds up to 6.144 Gbps independently from the selected silicon technology (Thursday May. 28, 2009)
  To enable higher performances and carrier grade capacity for multi-standard radio access networks Denmark based Radiocomp today released their CPRI v4.0 compliant IP core for LTE, WCDMA, CDMA and WIMAX supporting speeds up to 6.144 Gbps independently from the selected silicon technology. The compact and market-proven CPRI v.4.0 IP core has been adopted by companies such as Altera, mimoOn and Toshiba.
  
  
• Sarance Announces Availability of Complete Connectivity Solutions for Netronome's Network Flow Processors (Thursday May. 28, 2009)
  Sarance Technologies announced today the immediate availability of a complete connectivity solution for Netronome’s NFP-32xx family of Network Flow Processors™. The solution uses Sarance’s Interlaken IP Core (IIPC) products targeted for Field Programmable Gate Arrays (FPGAs) and provides a risk free solution for system developers using the NFP.
  
  
• Start-up claims breakthrough in reconfigurable logic (Thursday May. 28, 2009)
  A British company focused on dynamically reconfigurable logic technology, Akya (Selby, England), has launched its first device, dubbed the ART2.
  
  
• MindTree Lists Bluetooth Health Device Profile (HDP) (Thursday May. 28, 2009)
  MindTree today announced that its Bluetooth Health Device Profile (HDP) along with its EtherMind 2.1+EDR stack have been successfully listed as a qualified design component by the Bluetooth Special Interest Group (SIG).