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IP / SOC Products News

• Synopsys Releases DesignWare SATA IP for New SATA 6Gbps Data Transfer Rate (Wednesday May. 27, 2009)
  Synopsys today announced the availability of DesignWare® SATA AHCI host and device digital controller IP for the latest SATA 6 Gigabit per second (Gbps) data transfer rate as defined in the Serial ATA (SATA) Revision 3.0 specification.
  
  
• Rambus Unveils New Innovations for Main Memory (Tuesday May. 26, 2009)
  Rambus today unveiled a set of innovations that can advance computing main memory beyond current DDR3 data rate limits to 3200Mbps. These innovations, available for licensing, build on Rambus’ award-winning designs and include patented and patent pending technologies.
  
  
• CEVA and mimoOn to Collaborate on Development of LTE Baseband Solutions (Tuesday May. 26, 2009)
  CEVA and mimoOn today announced a collaboration to offer mimoOn's mi!MobilePHY™ advanced LTE software on CEVA's newest DSP core, the CEVA-XC™.
  
  
• IP Cores from Eureka Technologies Validated for Mentor Graphics' Precision FPGA Synthesis (Thursday May. 21, 2009)
  Eureka Technology has validated its NAND Flash controller, Secure Digital (SD, SDIO) and Multimedia Card (MMC) host and device controller IP cores for use with Mentor Graphics’ Precision® Synthesis FPGA flow. Designers can now use the advanced features of Precision Synthesis to achieve superior results with Eureka Technology’s IP cores for multiple FPGA device vendors.
  
  
• Unity Semiconductor, a Non-Volatile Memory Products Start-up, Exits Stealth Mode; World's First R/W Cross-Point Memory Array Requires No Transistor in Memory Cell (Thursday May. 21, 2009)
  The storage-class non-volatile memory (NVM) products company plans to achieve its objective using innovative, multi-layer, memory array architectures and a new breakthrough technology called CMOxTM, which is based on the use of new materials called conductive metal oxides into the semiconductor process that allows for ionic motion.
  
  
• Virage Logic Introduces First Commercially Available Multi-Time Programmable Non-Volatile Memory Solution at 65-Nanometer Low Power (Wednesday May. 20, 2009)
  Virage Logic today announced it has qualified its AEON(R) non-volatile memory (NVM) solution on TSMC's 65-nanometer (nm) Low Power (LP) process. As the industry's first multi-time programmable (MTP) logic NVM solution that is commercially available on a 65nm process, AEON further extends Virage Logic's NVM provider leadership position.
  
  
• GDA Technologies to Demonstrate 'Pravega' Family of Configurable USB 3.0 Controllers (Wednesday May. 20, 2009)
  GDA announced today to demonstrate "Pravega"--its USB 3.0 family of cores consisting of a highly configurable Superspeed device, hub and host controllers that are interoperable with third party PIPE compatible USB 3.0 PHY's running at 5 Gbits/s maximum speeds.
  
  
• eMemory Announces Availability of Low Cost OTP Mass Production Solution - NeoROM (Wednesday May. 20, 2009)
  eMemory today announced the roll-out of NeoROM, a powerful one-time programmable (OTP) solution for products in mass production.
  
  
• WideSail Technologies announces availability of their 10 Gb Ethernet FEC Decoder (Wednesday May. 20, 2009)
  WideSail announces general availability of their new NIAGARAflow LDPC error correcting decoder core for 10 GbE. This core outperforms the competition in every metric including power consumption, throughput, latency and output Bit Error Rate. It is compliant with the 10 GbE standard (IEEE 802.3an) but can also be adapted to many other similar applications.
  
  
• CEVA and Aricent to Demonstrate LTE PHY Platform for Cellular Handsets (Monday May. 18, 2009)
  CEVA and Aricent announced today that the companies will demonstrate a licensable IP platform for LTE baseband terminals based on a CEVA DSP core. The platform will showcase a CEVA DSP running several LTE physical layer functions purely in software.
  
  
• LogicVision Delivers Power-Aware Memory Self-Repair (Friday May. 15, 2009)
  LogicVision today announced a new power-aware version of its ETMemory™ built-in self-repair solution. On-chip memory test and repair is now fully compatible with the increasingly popular power management approach of using voltage islands to minimize power during functional operation.
  
  
• Synopsys Demonstrates DesignWare SuperSpeed USB 3.0 Controller IP at the SuperSpeed USB Developer's Conference (Thursday May. 14, 2009)
  Synopsys today announced its DesignWare® SuperSpeed USB 3.0 digital controller IP has tested successfully for interoperability with Texas Instrument's (TI) SuperSpeed USB 3.0 transceiver
  
  
• Enable Customers' Fastrack to USB 3.0, Faraday Pioneers to Launch Its USB 3.0 PHY in UMC 0.13um (Thursday May. 14, 2009)
  Faraday today announced the availability of the commercial USB3.0 physical layer (PHY) at UMC 0.13um high-speed (HS) process. This new component is based upon USB 3.0 version 1.0 specification, functionally and electrically, with the maximum speed of 5.0Gbps.
  
  
• TAKUMI Starts Licensing New Graphics Accelerator IP cores supporting 2D Vector Graphics (Monday May. 11, 2009)
  TAKUMI announced today that the company has started licensing GV500 and GV300, TAKUMI’s new graphics accelerator IP core supporting 2D Vector Graphics for use mainly in mobile phones and digital consumer electronics products. Both IP cores support the API standards for embedded systems: GV500 supports both OpenGL ES1.1 and OpenVG1.1 while GV300 supports OpenVG1.1.
  
  
• CEVA Partners with SMIC to Deliver Fully Functional Silicon for CEVA-TeakLite-III DSP Core (Monday May. 11, 2009)
  CEVA today announced the availability of fully-functional silicon for the 32-bit CEVA-TeakLite-III DSP core. The first chips were produced on SMIC's 90nm process and exceeded 600MHz.
  
  
• Qualcore initiates standard cell library development-new business wing (Thursday May. 07, 2009)
  QualCore Logic, an intellectual property (IP) and full-service, mixed-signal application specific integrated circuit (ASIC) realization company today announced that it added Standard cell library development as its new business wing.
  
  
• Achronix Taps Signali for 10/40/100Gbps Encryption IP in World's Fastest FPGAS (Thursday May. 07, 2009)
  Achronix Semiconductor, maker of the world's fastest field-programmable gate arrays (FPGAs), today announced the availability of new, high-performance Advanced Encryption Standard (AES) IP cores for its Speedster(TM) 1.5 GHz family.
  
  
• Sonics Answers Challenge of Designing Embedded SoCs Containing Multiple IP Blocks (Tuesday May. 05, 2009)
  Sonics has announced the Sonics Network for AMBA® Protocol or SNAP™. The product is a cost-effective, turn-key solution designed to simplify the on-chip bus design for complex embedded SoCs by turning multilayer bus designs into an IP block.
  
  
• DOLPHIN Integration Announces High Density BTF Library at 65 nm (Monday May. 04, 2009)
  Dolphin Integration extends at 65 nm the ultra High Density design of the “SESAME HD BTF” library, celebrated as the densest library on the market even before the advent of Back-Tracking Freedom (BTF).
  
  
• Passing the Compliance Test, Faraday Launch PCIe2.0 at 90nm (Tuesday Apr. 28, 2009)
  Faraday today announced that their PCIe GenII PHY, developed based on the PCI Express 2.0 specification, has passed PCI-SIG® APAC compliance test in April. This PHY is designed for UMC 90nm process and now available for ASIC customers.
  
  
• Digital Core Design Announces World's smallest and fastest 8051 Core (Friday Apr. 24, 2009)
  DCD releases World's smallest and fastest 8051 core. The 7150 ASIC gates for complete system including 8051-CPU, full duplex UART, Timers 0&1, Advanced Power Management Unit, eight I/O lines, eight external interrupts INT0-INT7 and 2-wire DoCD on-chip debugger is the best achievement on the IP Market. DT8051 runs Dhrystone 2.1 benchmark program 8.1 times faster than the original 80C51 at the same frequency.
  
  
• HDL Design House announces high performance AHB SPI flash memory controller (HIP 3100) (Wednesday Apr. 22, 2009)
  HDL Design House announces HIP 3100, a high performance AHB SPI flash memory controller. The SPI controller (HIP 3100) offloads AHB master and software from direct control of data transfers to/from flash memory subsystem, generation of SPI memory control signals, and increases overall memory subsystem performances.
  
  
• Sidense OTP Memory IP Enables 65nm Mobile Handset Chip (Tuesday Apr. 21, 2009)
  idense, a leading developer of Logic Non-Volatile Memory (LNVM) IP cores, today announced that its 1T-OTP one-time programmable (OTP) memory IP is available for customer designs at the 65nm process node. Sidense is the first embedded OTP vendor to announce high density (above 1 Mbit) product availability for both standard-logic and low-power 65nm implementation.
  
  
• Denali Software and Prism Circuits Prove DDR3 Controller-PHY Interoperability (Tuesday Apr. 21, 2009)
  Prism Circuits and Denali Software today announced interoperability validation of Prism's DDR3/2 Combo PHY with Denali's Databahn Memory Controller. Prism's fully-integrated solution complies with the latest DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3 DRAM devices to achieve datarates up to 2133Mbps.
  
  
• Kilopass Technology Expands Embedded Non-Volatile Memory Offering To Address Mobile, Consumer, and Computing Markets (Monday Apr. 20, 2009)
  Kilopass announced today BriteXPM, a new product family of one-time programmable (OTP) embedded non-volatile memory (NVM) for mobile, consumer and computing applications requiring faster random access time. As much as 40% improvement in random access time is achieved from the industrial and automotive product lines.
  
  
• TSMC/GUC 65LP ARM 1176JZF hardened cores Open Doors for 65nm Designers (Monday Apr. 20, 2009)
  TSMC and GUC today jointly announced that they have successfully implemented and obtained silicon samples of a high speed ARM 1176 core on TSMC’s 65 LP process, and an ultra low power ARM 1176 core which has been validated in GUC’s low power design platform. The first of the new developments is an ARM 1176JZF core capable of operation up to 1.10 GHz.
  
  
• ARM Announces Availability of Industry's Broadest 40nm G Physical IP Platform (Monday Apr. 20, 2009)
  ARM today announced the availability of the industry’s most comprehensive IP platform for TSMC’s 40nm G manufacturing process. This latest silicon-validated physical IP from ARM enables cost-effective development of performance driven consumer devices requiring advanced functionality without increasing power consumption.
  
  
• Vanguard Software Solutions Releases IP Cores for Panasonic AVC-Intra and H.264 CABAC; Transcoding Solutions for Video (Monday Apr. 20, 2009)
  Vanguard Software Solutions will showcase its latest H.264 technology at NAB 2009 trade show in Las Vegas, NV. Included are: support for Panasonic AVC-Intra and H.264 CABAC IP Cores for FPGA and custom ASICs; Real-Time AVC TRANSCODING required in Internet/Web Video Casting and H.264 SVC support required in video communications markets.
  
  
• CoreEL Technologies Creates Broadcast & Professional Video Grade H.264 High Profile Decoder Solution (Monday Apr. 20, 2009)
  CoreEL Technologies today announced the availability of the H.264 High Profile Decoder IP solution on Xilinx® Virtex® FPGAs, targeted for Professional decoder & Broadcast infrastructure markets. With a maximum resolution support of 1920x1080 (FullHD) at 60 frames per second, the IP introduces a new level of performance and functionality. The H.264 HP decoder supports 4:2:0, 4:2:2 and 4:4:4 chroma formats with programmable bit depth from 8-bit to 12-bits.
  
  
• Arasan Chip Systems Releases MIPI UniPro(sm) Software Stack Extending Its Total IP Solution (Thursday Apr. 16, 2009)
  Arasan announced the immediate availability of the Mobile Industry Processor Interface (MIPI(r)) UniPro Software Stack, a layered, kernel-level stack that eases the integration of UniPro into mobile platforms.