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IP / SOC Products News

• IP Cores, Inc. Announces an Ultracompact Version of the Snow 3G Cipher for 3GPP LTE (Thursday Apr. 16, 2009)
  IP Cores, Inc. has announced availability of a version of the SNOW 3G cipher core with very low gate count and power consumption. Along with the ultracompact AES cipher, this cores can be used in the new mobile communication devices for 3GPP LTE networks.
  
  
• PLDA Announces Industry's First SuperSpeed USB Host Bus Adapter Development Platform (Thursday Apr. 16, 2009)
  PLDA today announced that it has begun shipping the first SuperSpeed USB Host Bus Adapter (HBA) development platform. This HBA platform will enable leading-edge companies to develop and test USB 3.0 semiconductor designs or USB 3.0 software stacks more easily and efficiently, helping get them to market quicker.
  
  
• IP Cores, Inc. Announces a New Compact Version of the Elliptic Curve Crypto Accelerator (Thursday Apr. 16, 2009)
  IP Cores, Inc. had designed the ECC1 core that implements the necessary crypto functionality of the ECC algorithm (point multiplication and point verification functionality) and weighs in at less than 10,000 ASIC gates, 630 slices on Xilinx Virtex-5 devices, 2065 LE in Altera Cyclone II, 1137 ALUT in Altera Stratix II, and 7790 tiles for Actel ProASIC3.
  
  
• Synopsys Introduces Lower Power, High-Performance Architecture for AMBA 3 AXI On-Chip Interconnect (Wednesday Apr. 15, 2009)
  Synopsys today announced that it has enhanced its DesignWare® IP for the ARM® AMBA® 3 AXI™ interconnect with the industry's first hybrid architecture implementation, enabling dedicated high-performance and shared low-performance channels to be combined within a single AMBA 3 AXI on-chip interconnect.
  
  
• Lead Tech Design unveils its brand new range of microcontrollers for embedded applications (Tuesday Apr. 14, 2009)
  Lead Tech Design, which specializes in the design of ASIC/FPGA System-on-Chip (SoCs) and embedded software for Linux and Linux hard real time with Xenomai, is extending its offering with aRDAC, a brand new range of configurable microcontrollers, guaranteeing performance of 1 MIPS/MHz.
  
  
• IP Cores, Inc. Announces Ultracompact Version of Kasumi Cipher for 3G Devices (Tuesday Apr. 14, 2009)
  IP Cores, Inc. has announced availability of a version of the Kasumi cipher with very low gate count and power consumption. Along with the ultracompact AES cipher, this core can be used in the new mobile communication devices for 3G networks.
  
  
• Arasan Chip Systems Extends Its Strategic Mobile Initiative by Offering MIPI UniPro IP Solution (Friday Apr. 10, 2009)
  Arasan announced the immediate availability of the Mobile Industry Processor Interface (MIPI(r)) UniPro Controller IP, a layered, high-speed protocol that provides connectivity between applications processors and wireless, multimedia and mobile chipsets. As a leading provider of mobile IP, Arasan continues to strengthen its Strategic Mobile Initiative by expanding its MIPI IP portfolio with the UniPro IP.
  
  
• Dolphin Integration launches new microcontroller configurations (Friday Apr. 10, 2009)
  Dolphin Integration launches new microcontroller configurations and bundles of the i80251 legacy for best density and lowest power consumption.
  
  
• On2 Technologies Introduces Hantro 9170 HD Video Decoder (Friday Apr. 10, 2009)
  On2 today announced the availability of its ninth-generation hardware video codec design, the Hantro 9170. The design supports video playback up to full HD (1080p) resolution at 60 frames per second (fps) in multiple formats including MPEG-1, MPEG-2, MPEG-4, Sorenson Spark(R), H.263, H.264, VC-1 and REALVIDEO(R) 8, 9 & 10, as well as up to 66 megapixel JPEG still images.
  
  
• intoPIX enhances its multichannel JPEG 2000 codec IP-Cores to meet broadcasters' needs for live events (Wednesday Apr. 08, 2009)
  intoPIX presents its latest IPX-JPHD encoders and decoders for the broadcast industry. This new release not only delivers all the benefits of JPEG 2000, but is now able to provide the highest quality images for live events while meeting the tight latency requirements required to deliver this type of content.
  
  
• DCD Announces the 5th generation of World's fastest and most popular 8051 IP Core (Tuesday Apr. 07, 2009)
  Digital Core Design (DCD) today releases the 5th generation of World's fastest and most popular 8051 core. DP8051 runs Dhrystone 2.1 benchmark program 11.45 to 14.74 times faster than the original 80C51 at the same frequency.
  
  
• Gennum's Snowbush IP Group Enables Rapid Deployment of SATA and SAS 6 Gb/s Products (Monday Apr. 06, 2009)
  Gennum today announced that its Snowbush IP group has developed a SATA 6 gigabits per second (Gb/s) physical layer (PHY) IP block. The new IP also satisfies the stringent requirements of the latest Serial Attached SCSI (SAS) standard, SAS 2.0 (SAS-2). The SATA/SAS IP is being offered for manufacture in a variety of 65-nm and 45-/40-nm processes, including TSMC, as well as Common Platform Alliance members IBM, Chartered and Samsung.
  
  
• LogicVision Delivers New Embedded Boundary Scan Core Reuse Capability (Thursday Apr. 02, 2009)
  With new cores increasingly containing chip I/O circuitry and pads, LogicVision's new embedded boundary scan solution allows needed I/O DFT structures to be added directly into these cores rather than later at the top level during full chip integration.
  
  
• Denali Software First to Ship PCI Express 3.0 Controller IP Cores (Tuesday Mar. 31, 2009)
  Denali today announced availability and first customer shipments of the latest Denali Databahn(TM) controller IP cores, based on the current preliminary version of the PCI Express® (PCIe) 3.0 specification, for use in next-generation chip designs.
  
  
• Sonics Memory Scheduler Improves Memory Efficiencies in High-Bandwidth SoCs (Tuesday Mar. 31, 2009)
  Sonics has announced the availability of the MemMax Memory Scheduler 3.0, a DRAM access scheduler ideally designed for use with DDR2 and DDR3. geted at SoCs requiring high-bandwidth traffic management to the memory subsystem, the new MemMax Scheduler accelerates on-chip performance while easing design integration.
  
  
• Cambridge Consultants demonstrates Centaur GSM PHY reference design IP (Monday Mar. 30, 2009)
  Cambridge Consultants is demonstrating Centaur, a comprehensive GSM/GPRS/EDGE/E-EDGE physical layer (PHY) reference design. The novel reference design enables the development of advanced cellular base-stations and femtocells that incorporate 2G and 2.75G capability, addressing the ultra low-cost, mass-market and integration requirements of the developing world.
  
  
• Dolphin Integration Announces Memory Compiler Haumea at 65 nm (Friday Mar. 27, 2009)
  This generation of Haumea addresses the 65 nm LP process with compilers for both RAM and ROM.
  
  
• Arasan Chip Systems announces the World's First 75-in-1 Multi-Card Controller IP (Thursday Mar. 26, 2009)
  Building upon its leadership position in Secure Digital (SD/SDIO) solutions, Arasan has introduced yet another first – the 75-in-1 Multi-Card Controller. The family of controller IPs natively supports popular memory and I/O formats including SD, eSD, SDIO, MMC, eMMC, MS, MS Pro, CF and xD and their derivatives.
  
  
• MAZeT offers EnDat-IP for customized applications (Wednesday Mar. 25, 2009)
  MAZeT GmbH offers the IP core certified by the originator for the EnDat master (Heidenhain company) for implementation in FPGAs and ASICs. The serial communication interface for rotary and linear distance measuring systems was developed by MAZeT and maintained as product.
  
  
• Sarance Technologies Releases 40G/100G Ethernet IP for General Availability (Friday Mar. 20, 2009)
  Sarance Technologies announced today the immediate availability of HSEC (High Speed Ethernet Core), the world’s first commercially available Media Access Controller (MAC), Physical Coding Sublayer (PCS), and Multi Lane Distribution (MLD) IP conforming to the emerging 40Gigabit Ethernet (40GE) and 100Gigabit Ethernet (100GE) standard.
  
  
• MAZeT offers Interbus-IP for customized FPGA and ASIC implementation (Thursday Mar. 19, 2009)
  MAZeT GmbH offers IP cores for the Interbus protocol (SUPI4 / Phoenix Contact) for implementation in FPGAs and ASICs. The protocol chip for serial communication interfaces in automation technology was developed and maintained by MAZeT.
  
  
• MIPS Technologies Achieves Technical Milestones for USB 2.0 High-Speed PHY IP (Wednesday Mar. 18, 2009)
  MIPS Technologies today announced that its 40nm USB 2.0 High-Speed PHY IP achieved certification from the USB Implementers Forum (USB-IF) and met TSMC’s TSMC9000 standards in its 40nm LP process.
  
  
• Faraday Offers 0.13um miniIO with around 40% Area-Saving and Robust ESD Performance (Wednesday Mar. 18, 2009)
  Faraday today announced the availability of its innovative IO offering at 0.13um, miniIO™. Compared with general IO pads, the advantage of Faraday's miniIO™ is its area reduction, up to 40% for a pad-limit design with 200 pins, and still keeping the same programming IO functionality, while achieving robust ESD performance.
  
  
• Imagination Technologies launches advanced, highly-efficient POWERVR SGX543MP multi-processor graphics IP family (Monday Mar. 16, 2009)
  Imagination Technologies announces further details of the first POWERVR SGX graphics IP core with multi-processor (MP) core support. The technology, henceforth POWERVR SGX543MP, is being delivered to customers in SGXMP2 (two-core) to SGXMP16 (16-core) variants.
  
  
• Silistix Announces Industry's First Mixed Synchronous/Asynchronous Network-on-Chip Solution in CHAIN(R)works 3.0 (Monday Mar. 16, 2009)
  Silistix Inc. today announced CHAINworks 3.0, enabling architects and designers of complex chips to synthesize Networks-on-Chip (NoC) using both synchronous and asynchronous circuit techniques.
  
  
• Full debugging features at the lowest silicon cost with Dolphin Integration 16-bit microcontroller thanks to the innovative Virtual Clone (Friday Mar. 13, 2009)
  Offering to 8051 software developers a complete set of debugging features - unlimited watchpoints, unlimited breakpoints, unlimited trace memory depth, etc - at practically no silicon expense is achievable with the patented solution of Virtual Clone.
  
  
• Evatronix Releases High Resolution Display Controller IP Core (Tuesday Mar. 10, 2009)
  Evatronix announced today the release of DISPLAY-CTRL – a High Resolution Display Controller IP core for PC, home video, mobile and industrial applications. The controller supports all common display formats, from QVGA to WUXGA and Full HD resolutions.
  
  
• CebaTech Takes Intellectual Property Business to the Next Level with CebaRIP Rapidly Tunable Cores (Tuesday Mar. 10, 2009)
  CebaTech has announced that it is taking its IP business to the next level with a library of rapidly tunable IP cores, CebaRIP cores. The initial offering is targeted at the IP realization of standard algorithms used extensively in storage, storage area network (SAN), network-attached storage (NAS), and networking applications, including compression, encryption, fingerprinting, and more. In addition to these standard CebaRIP cores,
  
  
• Synopsys DesignWare USB 2.0 nanoPHY and PCI Express 1.1 PHY IP First to Achieve Compliance in UMC's 65-Nanometer Process Technologies (Tuesday Mar. 10, 2009)
  Synopsys, Inc. , a world leader in software and IP for semiconductor design and manufacturing, today announced that the DesignWare® USB 2.0 nanoPHY IP and PCI Express® 1.1 PHY are the first IP cores to achieve compliance in UMC's 65-nanometer (nm) SP and LL process technologies.
  
  
• LogicVision Announces Memory BIST & Repair Solutions for 45nm SOI Foundry Customers (Tuesday Mar. 10, 2009)
  LogicVision today announced that IBM has included LogicVision's ETMemory(TM) memory BIST and on-chip self-repair solution for embedded memory test and yield improvement within its advanced 45nm silicon-on-insulator (SOI) semiconductor foundry flow.