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IP / SOC Products News

• POWERVR SGX520, the world’s smallest OpenGL ES 2.0 core achieves Khronos conformance (Thursday Nov. 20, 2008)
  POWERVR SGX520 is the world’s smallest 3D graphics processor solution to achieve OpenGL ES 2.0 conformance - reinforcing POWERVR’s credentials as the leading mobile and embedded graphics acceleration solution. POWERVR SGX520 is less than 2.6mm2 in TSMC 65LP process.
  
  
• Imagination announces latest POWERVR VXE video encoder IP cores (Wednesday Nov. 19, 2008)
  Imagination Technologies announced today the availability of two new IP cores in the POWERVR™ VXE video encoder family. POWERVR VXE251 and VXE280 deliver multi-standard encode at SD and HD resolutions respectively
  
  
• GDA Technologies Ships Configurable USB 3.0 Controller (Tuesday Nov. 18, 2008)
  GDA Technologies announced plans today to ship “Pravega”--its USB 3.0 family of cores consisting of a highly configurable Superspeed device and host controllers that are interoperable with third party USB 3.0 PHY’s running at 5 Gbits/s maximum speeds.
  
  
• Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000AXI for the AMBA 3.0 Interconnect (Tuesday Nov. 18, 2008)
  The DB9000AXI IP Core targets TFT LCD panels with 1 Port of 18-bit digital (6-bits/color) or 24-bit digital (8-bits/color) interface or a 2 Port interface, with each port up to 24-bit digital (8-bits/color). The DB9000AXI, with its 64-bit AXI interface and programmable 2 Port TFT LCD Panel Interface, specifically targets high resolution displays.
  
  
• sRAM generator HAUMEA at 90 nm on DOLPHIN Integration's website (Tuesday Nov. 18, 2008)
  The winning performance mix BCD, Best for Consumption and Density, is heralded by the new sRAM Haumea generator at 90 nm LP process.
  
  
• Wipro-NewLogic delivers WLAN and Bluetooth RF IPs in TSMC 90nm (Monday Nov. 17, 2008)
  Wipro-NewLogic today announced that its Bluetooth 2.1+Enhanced Data Rate RF IP (BOOSTTM RF) and IEEE 802.11a/b/g WLAN RF IP (WiLDTM90 RF) are silicon proven in TSMC 90nm.
  
  
• Faraday Technology and Fresco Logic Partner to Validate SuperSpeed USB PHY (USB 3.0) with SuperSpeed Digital xHCI Host and Device Controller (Friday Nov. 14, 2008)
  Faraday Technology and Fresco Logic today announced a partnership to validate the integration of Faraday's USB 3.0 (SuperSpeed USB) PHY IP (Physical Layer IP) with Fresco Logic's USB 3.0 xHCI Host and Device Controller IP.
  
  
• Microtronix updates Multi-port SDRAM Memory Controller IP Cores to support Stratix III and Arria GX FPGA devices. (Thursday Nov. 13, 2008)
  To improve performance of the Memory Controller IP cores, the internal structure was redesign to improve clock distribution networks and incorporate new architectural features available in Stratix III devices. These design changes improved timing closure and boosted DDR2 memory performance from 333 MHz in a Stratix II to over 400 MHz in a top speed grade Stratix III device.
  
  
• PLDA Announces SuperSpeed USB IP Solutions, Providing Designers With Immediate Ability to Integrate USB 3.0 Host And Device Functionality (Thursday Nov. 13, 2008)
  PLDA today announced the immediate availability of a new line of SuperSpeed USB IP products designed for ASIC and FPGA.
  
  
• Synopsys Announces Complete SuperSpeed USB IP Solution Consisting of Device Controller, PHY and Verification IP (Wednesday Nov. 12, 2008)
  Synopsys today announced a complete, single vendor SuperSpeed USB IP solution consisting of the DesignWare® device controller, PHY and verification IP.
  
  
• Forty CAST IP Cores Validated for Mentor Graphic's Precision FPGA Synthesis Tool (Wednesday Nov. 12, 2008)
  CAST, Inc. is working with Mentor Graphics® to ensure that users of the company’s FPGA synthesis design flow have a superior experience using CAST’s IP cores.
  
  
• Coreworks introduces SideWorks, a high-performance, small footprint and ultra low power licensable Digital Signal Processing (DSP) Core (Tuesday Nov. 11, 2008)
  SideWorks™ creates breakthrough in addressing Audio and Video applications in demand of area-optimized, performance and optimal power consumption
  
  
• eASIC and Video-Cores Deliver Low-Cost Video IP Solutions (Tuesday Nov. 11, 2008)
  eASIC and Video-Cores today announced the immediately availability of proven video IP cores for eASIC’s low-cost Nextreme ASICs.
  
  
• Kilopass Technology Announces 30% Price Reduction In Embedded Non-Volatile Memory for Integrated Circuit (IC) Design (Monday Nov. 10, 2008)
  Based on five years of product success, SnapXPM comprises a series of pre-configured non-volatile memories across more than 10 semiconductor process technologies. The off-the-shelf products are available now and are priced at 25% to 30% lower than the existing XPM products.
  
  
• ARM Announces Industry's First Silicon-on-Insulator Physical IP Library for IBM's New 45nm SOI Foundry (Monday Nov. 10, 2008)
  ARM today announced the industry's first Silicon-on-Insulator (SOI) physical IP library including standard cell, memory and I/O libraries for IBM's fully enabled 45nm SOI foundry, also announced today.
  
  
• Northwest Logic Announces the Immediate Availability of x8 PCI Express 2.0 Solution For Xilinx Virtex-5 FXT FPGA Platform (Monday Nov. 10, 2008)
  Northwest Logic announces the immediate availability of a high-performance, hardware-proven x8 PCI Express(R) 2.0 Solution for Xilinx's Virtex(R)-5 FXT FPGA platform. This solution combines Northwest Logic's full-featured x8 PCI Express 2.0 cores and software to provide a complete, pre-packaged x8 PCI Express 2.0 solution.
  
  
• Manycore Processor Adoption Barriers Lowered by New Development Tools from Plurality (Thursday Nov. 06, 2008)
  The tools will facilitate the evaluation and widespread adoption of Plurality’s technology. Manycore architecture – from tens to thousands of cores per processor – is widely acknowledged as the natural evolution of multicore processing. HAL processors will offer the highest performance at the lowest price per watt per square millimeter of any chip-level shared memory machine currently on the market.
  
  
• Evatronix upgrades its SDIO Host Controller with the full support for CPRM, MMC 4.2, and SDIO specification rev. 2.0. (Monday Nov. 03, 2008)
  Support for MMC 4.2 guarantees the IP core’s compatibility with the newest MMC-Plus memory cards, and thus increases the maximum data transfer rates to 400 Mbit/s.
  
  
• Digital Blocks Announces the TFT LCD Controller Reference Design for Altera FPGA Development Kits based on the DB9000AVLN LCD Controller IP Core (Friday Oct. 31, 2008)
  Digital Blocks today announces the TFT LCD Controller Reference Design centered on Digital Blocks DB9000AVLN TFT LCD Controller IP Core and Altera’s FPGA Development Kits.
  
  
• Arasan Chip Systems Builds On Strategic Mobile Initiative With MIPI CSI-2 IP Solution Release (Friday Oct. 31, 2008)
  Arasan Chip Systems today announced the first fully compliant Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI) IP commercially available on the market.
  
  
• Synopsys Announces Availability of DesignWare SATA PHY IP in SMIC 130-nm Process Technology (Thursday Oct. 30, 2008)
  Synopsys today announced the immediate availability of the silicon-proven DesignWare® SATA PHY IP for SMIC's popular 130 nanometer (nm) process technology.
  
  
• Evatronix introduces a Hi-Speed USB Embedded Hub Controller (Wednesday Oct. 29, 2008)
  USBHS-HUB, due to its USB Specification Rev. 2.0 compliance, supports all USB transfer speeds - High, Full and Low. For seamless communication between the USB host and devices operating at different data transmission rates the hub implements an integrated Transaction Translator which takes care of proper interpretation of high speed signaling for components operating at full and low speeds.
  
  
• MoSys 1T-SRAM Embedded Memory Technology Meets TSMC 90 Nanometer eDRAM Process Standards (Tuesday Oct. 28, 2008)
  MoSys today announced it has achieved Level III and IV verification of its 1T-SRAM embedded memory technology on TSMC's 90 nanometer (nm) General Purpose eDRAM process by the foundry's IP Alliance program.
  
  
• Xilinx and EB Drive OBSAI Standard Adoption for Wireless Infrastructure (Thursday Oct. 23, 2008)
  Joint interoperability testing of Xilinx LogiCORE IP for OBSAI RP3-01 completed with EB Base Station Interface Tester to enable faster, lower cost development of wireless base stations
  
  
• Arteris Delivers Major Productivity Features for Its Network-on-Chip Interconnect IP and Toolset (Wednesday Oct. 22, 2008)
  NoC Pioneer's Seventh Major Production Release Includes Advanced Memory Traffic Support, System Verilog-based Verification Tool and Multi-Voltage Support
  
  
• IPextreme Delivers Free ColdFire Processor for Altera Cyclone III FPGA (Tuesday Oct. 21, 2008)
  IPextreme today announced immediate availability of the V1 ColdFire® IP core optimized for Altera Cyclone III devices. The V1 ColdFire FPGA CIII Processor core can be downloaded free of charge.
  
  
• Fresco Logic Demonstrates Industry's First SuperSpeed USB Extensible Host Controller Interface (xHCI) (Tuesday Oct. 21, 2008)
  Fresco Logic will demonstrate a SuperSpeed USB (USB 3.0) xHCI host solution on its hardware development platform in the USB 3.0 Promoter Group booth at the Intel Developer Forum (IDF) in Taiwan.
  
  
• Evatronix Application-debugging Support Environment for 8051 and 68000 compliant IP cores improved with trace and TCP/IP support (Tuesday Oct. 14, 2008)
  The newest release of the EASE enhances its predecessor functionality by two new features: the configurable real-time trace and the TCP/IP support, hence providing customers with better, faster and more convenient interface between the hardware prototype and the embedded software development environment.
  
  
• Alma Technologies to integrate Scalado SpeedTags technology in its JPEG products (Monday Oct. 13, 2008)
  Scalado and Alma Technologies have today announced details of the first JPEG compression IP core supporting Scalado SpeedTags™ technology.
  
  
• Imagination Technologies extends successful POWERVR SGX53x family (Tuesday Oct. 07, 2008)
  POWERVR SGX531 takes the already industry-leading capabilities of POWERVR SGX IP cores to another new level with an upgraded 128-bit internal bus architecture and related enhancements to maximise performance when integrated in the latest SoCs.