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IP / SOC Products News

• MIPS Technologies Announces USB PHY Breakthroughs (Monday Aug. 11, 2008)
  MIPS Technologies today introduced the industry's first 40nm USB PHY IP core and first USB-certified 1.8v 45nm USB PHY IP core.
  
  
• Cosmic Circuits Announces Validation as a Common Platform Solution Provider of New Analog IP Cores (Friday Aug. 08, 2008)
  Cosmic Circuits, a leading provider of differentiated Analog and Mixed-signal IP, today announced the validation of silicon IP cores for 90nm Common Platform™ technology. This includes IP cores for high-performance power-regulation and analog-to-digital conversion that are used predominantly in chips for portable consumer products and communications.
  
  
• Great River Technology Releases ARINC 818 Video IP Core for Xilinx and Altera FPGAs (Thursday Aug. 07, 2008)
  Great River Technology Releases ARINC 818 Video IP Core for Xilinx and Altera FPGAs Great River Technology released the first ARINC 818 IP core for aerospace and military video applications. The IP core targets both Xilinx and Altera FPGAs and drastically reduces the effort of implementing an ARINC 818 interface into new applications.
  
  
• CAST Offers Special System Library IP Package for AMBA-Based FPGAs and SoCs (Thursday Aug. 07, 2008)
  CAST and SoC Solutions today announced that the complete PiP-AMBA system infrastructure library is now available in a special website-only package, with a simplified license for easy purchase, and a reduced US price of $10,000.
  
  
• UMC's Embedded DRAM, URAM(TM) Proven in 65nm Customer Silicon (Monday Aug. 04, 2008)
  Pure-Play Foundry Industry's Only Proprietary Embedded DRAM Solution Enables Performance, Size and Cost Advantages for SoC Products
  
  
• Evatronix announces T8051 - the world's smallest 8051 ISA-compliant IP Core. (Friday Aug. 01, 2008)
  A significant decrease in the number of gates does not affect performance, which surpasses the original MCU by more than 4 times.
  
  
• Denali Announces Complete Bundle of I/O Virtualization Technology Solution With PureSpec PCI Express Verification IP (Thursday Jul. 31, 2008)
  Industry-Leading Verification IP Solution Provides Full Specification Support Of PCI-SIG IOV Technology Standard
  
  
• Denali Releases ONFi 2.0 Memory Controller and Verification Suites (Thursday Jul. 31, 2008)
  FlashPoint Platform Supports ONFi 2.0 NAND Flash Technology for PCIe-based Memory Systems
  
  
• Vivante Brings GPU IP Solutions to MIPS Alliance Program (Wednesday Jul. 30, 2008)
  Vivante will optimize its HD Visual Reality and Mobile Visual Reality line of 2D and 2D/3D graphics processor IP solutions, for integration in designs using the MIPS32® 24K® and MIPS32® 24KE™ cores, which are widely used in media server, DVD, set-top box and mobile solutions.
  
  
• MOSAID to Unveil Enhanced Flash Architecture for Solid State Drives (Tuesday Jul. 29, 2008)
  MOSAID's HLNAND(TM) Flash is a new architecture and interface for high-performance Flash memory.
  
  
• Vivante's OpenGL ES 2.0 Conformance Submission First to Support Depth Texture Extension (Monday Jul. 28, 2008)
  Vivante has submitted conformance results based on the GC600 2D/3D GPU IP core for the OpenGL ES 2.0 conformance test to the KhronosTM Group for review.
  
  
• MIPS Technologies' Silicon-proven GPS RF Tuner IP Reduces Risk for Developers of Next-generation Devices with GPS (Monday Jul. 28, 2008)
  The silicon-proven, integrated low-noise RF front-end for GPS receivers in the L1 band enables embedded system designers to decrease costs and time-to-market for next-generation devices incorporating GPS.
  
  
• Synopsys Announces Availability of New Fully Synthesizable PowerPC Cores (Wednesday Jul. 23, 2008)
  Synopsys today announced the availability of fully synthesizable implementations of the IBM PowerPC® 460 and cache configurable PowerPC 405 embedded microprocessor cores as components of the DesignWare® Star IP program.
  
  
• DOLPHIN Integration launches the 32-bit challenger: FlipAPS-32, a processor tiny enough for embedding controls (Monday Jul. 21, 2008)
  Dolphin Integration and Cortus SA are partnering for this 32-bit processor with the silicon area of a 16-bit core and with a minimal power consumption, but with the largest addressing capability.
  
  
• Denali Announces New LPDDR2 Memory Controller and PHY Solution (Monday Jul. 21, 2008)
  First Provider of Memory Controller and PHY Solution to Support LPDDR2 in Next-Generation Mobile and Embedded Applications
  
  
• Algotronix adds thermal signaling to IP core DesignTag (Friday Jul. 18, 2008)
  Algotronix has added 'thermal signaling' to DesignTag, an active digital circuit element that can be designed-in to ICs and FPGAs and detected through-package by an external scanner.
  
  
• eInfochips announces SPI4.2 and CCIR656 Stream Generator Design IP (Friday Jul. 18, 2008)
  eInfochips today announced the availability of OIF (Optical Internetworking forum) compliant SPI4.2 design IP (System packet interface Level 4 Phase 2) and ITU-R BT 601 and ITU-R BT 656 compliant CCIR 656 stream generator design IP.
  
  
• Digital Blocks Announces I2C-Master Controller IP Core Family with the availability of the DB-I2C-M for the ARM AMBA 2.0 APB and Altera NIOS II Avalon Interconnects (Friday Jul. 18, 2008)
  The DB-I2C-M targets High-Performance Embedded Processor designs requiring a Smart I2C Controller in a small VLSI footprint
  
  
• Athena Announces Cryptographic-Grade Random Number Generator (Tuesday Jul. 15, 2008)
  Portable to any semiconductor process, Athena's TeraFire RNG cores are a fast and reliable way to incorporate cryptographic-grade random numbers into your SoC design.
  
  
• Synopsys Broadens DesignWare SATA Solution With Device IP (Monday Jul. 14, 2008)
  Comprehensive SATA IP Portfolio Including Device, Host, PHY and Verification IP Passes Interoperability Testing, Reducing Integration Risk for SoC Designs
  
  
• Silicon Image Offers Mobile Phone Manufacturers a Better Way to Implement an HDTV Connection (Monday Jul. 14, 2008)
  Silicon Image today announced its ultra-low-power interface solution consisting of a VastLane(TM) SiI9206 HDMI(TM) transmitter PHY semiconductor and a companion link layer IP core for use in consumer mobile device applications.
  
  
• ARM Mali-200 GPU World's First To Achieve Khronos OpenGL ES 2.0 Conformance At 1080p HDTV Resolution (Monday Jul. 14, 2008)
  The ARM® Mali™-200 graphics processing unit is the first GPU on today’s market to pass Khronos conformance testing at up to 1080p HDTV resolutions.
  
  
• Virage Logic Expands Memory Interface Product Portfolio With New DDR3 Solution That Supports Speeds Up to 1.6 Gb/s (Monday Jul. 14, 2008)
  Comprising a DRAM memory controller, digital PHY, DLL, and I/O, Intelli DDR3 provides a true System Aware IP(TM) solution that is able to mitigate and manage the high-speed interconnect effects that must be addressed at the package as well as board level.
  
  
• A New Era for Dolphin Integration's Embedded Memories (Monday Jul. 14, 2008)
  Dolphin Integration is announcing a blockbuster sRAM Trio for embedding in circuits at 130 nm in G process and at 90 nm in LP process.
  
  
• Chips&Media unveils Boda7503, High-Definition video IP solution including AVS (Friday Jul. 11, 2008)
  Chips&Media’s Boda7503 is a highly optimized decode core supports H.264, MPEG-2, MPEG-4, VC-1, RealVideo, MJPEG in addition to AVS up to HD(1080p).
  
  
• Cambridge Consultants XAP5 core sets new standard for 16-bit processors (Thursday Jul. 10, 2008)
  XAP5 combines the economy of a 16-bit data word with a 24-bit address space for large programs up to 16 Mbytes, which suits devices designed for data-centric communications applications in markets such as consumer, industrial and retail.
  
  
• Dolphin Integration announce a breakthrough in silicon IP for power management (Monday Jul. 07, 2008)
  SRO and SRI Switching Regulators innovate with their inductorless architecture, a technique used for the first time in silicon IP.
  
  
• Evatronix adds 6502 and 80186XL ISA-compliant IP cores to its portfolio (Monday Jul. 07, 2008)
  Both solutions add up to Evatronix obsolete part replacement IP core family.
  
  
• Sonics Eliminates Barriers to Multichannel Memory Management Industry Adoption With New Interleaved Multichannel Technology(TM) (Tuesday Jul. 01, 2008)
  IMT utilizes an innovative memory interleaving methodology as a foundation for managing up to 8 external DRAM channels. User-controlled interleaving addresses the key challenge of adopting multichannel architectures: ensuring that the memory traffic is divided evenly among the channels.
  
  
• New SonicsSX SMART Interconnect Solution Solves Memory Performance Problem for High Quality, High Definition Video SoCs (Tuesday Jul. 01, 2008)
  Designed for SoCs requiring high quality, high definition, or HQHD, video support, SonicsSX accelerates video performance and eases global integration of intellectual property cores and subsystems onto a single chip.