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IP / SOC Products News

• Wipro-NewLogic and Alereon Demonstrate Wireless USB Dual Role Device Solution (Monday Jan. 08, 2007)
  Based on Certified Wireless USB Technology from the USB Implementers Forum (USBIF), Wipro-NewLogic’s DRD MAC IP core acts as Wireless USB Device as well as Wireless USB Embedded Host. For the demo, one Wireless USB setup is configured as Embedded Host MAC (attached to a PC), the second is configured as a Device MAC (attached to a mobile handset). With this setup images and files are transferred through Wireless USB protocol.
  
  
• GDT introduces H.264 encoder Silicon IP (Thursday Jan. 04, 2007)
  GDT-H264EBH, highly integrated silicon IP core, is fully compliant to the emerging ISO/IEC 14496-10 (ITU-T H.264 or MPEG-4 Part10 /AVC) video coding standard. It is designed to offer maximum performance and compression quality at the lowest possible bit-rate.
  
  
• NovoBlox OTP Memory Qualifies at Jazz Semiconductor (Wednesday Jan. 03, 2007)
  Novocell Semiconductor announced that its NovoBlox OTP Memory has been silicon validated in Jazz Semiconductor’s CA18HR 0.18-micron process.
  
  
• Digital Core Design Announces Availability of DZ80, a 8-bit Microprocessor IP Core (Tuesday Jan. 02, 2007)
  It is an immediate substitute which is 100 percent compatible with pin, software in respect to a standard Z80. DZ80 is a single-chip 8-bit embedded processor dedicated for operation with fast (typically on-chip) and slow (off-chip) memories.
  
  
• ASIC Architect Announces Availability of Configurable AMBA 3 AXI Bridge for DDR Controller Cores (Tuesday Dec. 26, 2006)
  ASIC Architect Expands its DDR Offerings with AMBA© 3 AXITM Bridge for DDR Controller Cores
  
  
• Dolphin Integration Announces their new generation of CODEC providing a Signal to Noise Ratio of 100 dB (Thursday Dec. 21, 2006)
  a silicon area of 4.2 mm2 for the whole CODEC at no extra fabrication cost: 5 metal layers over a logic process at 0.13 um
  
  
• Array Electronics's DDR SDRAM Controller XS receives Xilinx AllianceCORE product certification (Thursday Dec. 21, 2006)
  Array Electronics, one of the leading european suppliers of Intellectual Property (IP) cores for the programmable logic market, has received AllianceCORE product certification from Xilinx for its DDR SDRAM Controller XS core, the flagship product of the family of DRAM memory controller IP cores of the company
  
  
• ARM Announces First Production-Ready DDR1 And DDR2 Memory Interface IP On TSMC 90-Nanometer Process (Tuesday Dec. 19, 2006)
  The ARM Velocity DDR1/2 memory interface is the first 90-nm production-ready IP to pass TSMC's IP quality assurance test
  
  
• Faraday Adds Fast Ethernet PHY and Controller Cores to its Licensable IP Portfolio (Tuesday Dec. 19, 2006)
  Faraday's 0.18µm ,and 0.13µm ,Fast Ethernet PHYs and the 10/100/1000 MAC digital IP cores have been production-proven and can be licensed immediately with design kits; the test chip of 90 nm PHY is expected to be available in February, 2007
  
  
• Imagination Technologies' Multi-Standard Video Core Passes Allegro H.264 Test Suite (Monday Dec. 18, 2006)
  PowerVR MSVDX IP Shipping Now
  
  
• Sarance Technologies Delivers Interlaken Protocol IP Core for Xilinx Virtex-5 FPGAs (Monday Dec. 18, 2006)
  New IP Core Implements Next Generation High-Speed Serial Chip-To-Chip Packet Interface
  
  
• Denali Launches MLC NAND Flash Solutions for SoC Designs (Monday Dec. 18, 2006)
  Databahn NAND Flash Controller IP and Spectra NAND Flash Management Software Speeds Deployment of MLC NAND Flash Memory in Electronic Products
  
  
• ASIC Architect Announces the Availability of Configurable AMBA3 AXI Bridge for PCI Express Controller Cores (Monday Dec. 18, 2006)
  This solution will enable SoC designers to plug-in PCI Express Controller Core into AMBA3 AXI system bus, and mitigate the implementation risk and time-to-market challenges
  
  
• Jetstream Media Technologies Announces a Full Line of Security IP Cores for ASIC and FPGA (Thursday Dec. 14, 2006)
  The broad product line implements many security standards including AES, AES-CCM, AES-GCM, XEX-AES, secure hashing algorithms, Triple-DES and public key cryptography for applications ranging from secure wireless communication, storage server to network devices.
  
  
• PLDA Announces PCI-SIG Compliant Programmable Switch IP for PCI Express (Thursday Dec. 14, 2006)
  The Programmable Switch IP, which includes an upstream and downstream instance of PLDA's XpressRich shared-silicon IP Controller connected with a glue logic, is a highly configurable solution suitable for connecting x1, x4, and x8 lane components
  
  
• Arasan Announces Support for SDIO Version 2.0 in its SDIO Device IP (Tuesday Dec. 12, 2006)
  Arasan provides a Total Technology Solution to all its licensees including IP source code, a test environment, sample device drivers, synthesis scripts, and complete technical documentation.
  
  
• IPextreme to Bring Expanded Portfolio of Advanced Infineon IP to Rapidly Growing Automotive Electronics Market (Monday Dec. 11, 2006)
  IPextreme will market, license and support Infineon’s MultiCAN, MCDS, MLI and MSC interface blocks to system on chip (SoC) designers seeking to integrate state-of-the-art network, debug, and fast serial interface technology
  
  
• Virage Logic and Tensilica Introduce Core-Optimized IP Kits for Tensilica's Diamond Standard Processors (Monday Dec. 11, 2006)
  Kits are Optimized to Meet Area, Performance and Power Requirements
  
  
• Mentor Graphics Introduces its High-Speed USB-Certified PHY for Embedded Host Applications in the SMIC 0.13 micron Process (Tuesday Dec. 05, 2006)
  This “proven-in-silicon” USB 2.0 PHY implements a UTMI+ Level3 USB Transceiver Macrocell Interface, and offers support for device, host, embedded host and OTG USB controllers
  
  
• Chipidea Achieves Industry's First USB High Speed PHY Certification in TSMC 65nm Technology (Tuesday Dec. 05, 2006)
  Benchmark Assures PHY Quality for Small Area, Low Cost SoC Integration
  
  
• True Circuits Announces New Line of 65nm Timing IP; Customers' Product Shipments Planned for 2007 (Monday Dec. 04, 2006)
  IP Suits High-Speed Timing Applications Requiring Low Jitter, Low Power and Fast Restarts
  
  
• Novelics Introduces Silicon-Proven coolSRAM-1T for SoC Designers with Large Embedded Memory Needs (Monday Dec. 04, 2006)
  A leading provider of multi-standard semiconductor application-specific integrated circuits for Mobile TV and Digital Audio broadcast standards started production ramp up of chips with the Novelics’ embedded coolSRAM-1T
  
  
• Z-RAM Gen2 Ultra-Dense Memory Technology from ISi Significantly Improves Speed and Power (Monday Dec. 04, 2006)
  Z-RAM technologies achieve world-leading density and performance by using a single transistor as a memory bitcell, which is made possible by harnessing the Floating Body Effect found in circuits fabricated using SOI (silicon-on-insulator) wafers.
  
  
• Tensilica Introduces Four Video Processor Engines Including Main Profile H.264 Support (Monday Dec. 04, 2006)
  New Drop-In Diamond Standard Processors for H.264, VC-1/WMV9, MPEG-4 and MPEG-2 Video for SOC Design
  
  
• Tensilica Introduces Xtensa LX2 and Xtensa 7 Configurable Processors (Monday Dec. 04, 2006)
  New Cores Extend Tensilica's Configurable Processor Technology Leadership
  
  
• Low Power Hard Core Diamond Standard Processor for TSMC 0.18-micron Technology Available Through Global Unichip (Monday Dec. 04, 2006)
  First Hardened Diamond Standard Processor Available; Reduces SOC Integration Cost
  
  
• Arasan Announces Support for Part A2 of the SDIO Version 2.0 Specification (Friday Dec. 01, 2006)
  The Part A2 enhancement extends the basic DMA Part A1 capability to an advanced Scatter-gather method. The new method improves the performance allowing transfer to/from multiple memory locations in a single DMA transaction.
  
  
• Chips&Media's BodaHx5 Multi Standard HD (High Definition) decoder IP solution provides customers with superior features and high quality video for mobile and home appliance market (Thursday Nov. 30, 2006)
  The new BodaHx5 multi-standard HD decoder IP solution offers an impressive array of video features including support for MPEG-2 MP@HL / H.264 HP@L4.1 /VC-1 AP@L3.0 video decoding at 30fps while only running at 133MHz internal clock frequency
  
  
• Evatronix Partners with JMicron to Deliver Total USB Solutions (Wednesday Nov. 29, 2006)
  Silicon-proven USB controller IP cores and PHYs available for multiple CMOS processes
  
  
• IP Cores, Inc. Announces New High-Speed IP Combo XEX-AES Family of Cores Supporting New IEEE P1619 Draft Standard (Wednesday Nov. 29, 2006)
  IP Cores, Inc. announces a family of silicon IP cores supporting new IEEE P1619 standard draft. Starting from 30K ASIC gates and delivering up to 70 Gbps throughput, XEX3 cores provide a compact and flexible solution for an SoC designer working on a secure storage solution.