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IP / SOC Products News

• Moortec announce their Embedded In-Chip Monitoring Subsystem on TSMC 12FFC (Monday Jan. 15, 2018)
  Moortec, specialist in embedded in-chip sensing, is pleased to announce the availability of their easy to integrate, high accuracy, embedded monitoring subsystem on TSMC’s 12nm FinFET Compact process technology (FFC).
  
  
• videantis introduces new processor and tools for deep learning (Tuesday Jan. 09, 2018)
  videantis today announced its new v-MP6000UDX visual processing architecture and v-CNNDesigner tool. The new processor increases deep learning algorithm performance by up to three orders of magnitude, while maintaining software compatibility with the already very powerful and successful v-MP4000HDX architecture.
  
  
• Dolphin Integration paves the way for the next generation of Digital microphones "CoolMic" (Monday Jan. 08, 2018)
  Dolphin Integration introduces Rooster Silicon IP to design “CoolMic – A high performance & ultra low power Digital Microphone” for Voice First devices
  
  
• CEVA Unveils NeuPro - A Family of AI Processors for Deep Learning at the Edge (Friday Jan. 05, 2018)
  CEVA today unveiled NeuPro™, a powerful and specialized Artificial Intelligence (AI) processor family for deep learning inference at the edge. The NeuPro family of processors is designed for smart and connected edge device vendors looking for a streamlined way to quickly take advantage of the significant possibilities that deep neural network technologies offer.
  
  
• Hardent IP Portfolio Supports New Features of HDMI 2.1 Specification (Thursday Jan. 04, 2018)
  Hardent today announced plans to support HDMI controller manufacturers with adopting the new HDMI 2.1 specification Hardent’s portfolio of VESA Display Stream Compression (DSC) and Reed-Solomon Forward Error Correction (FEC) IP cores will accelerate product development time and enable companies to take advantage of key new features of HDMI 2.1 to develop next-generation displays.
  
  
• CEVA's Bluetooth 5 Low Energy IP certified with Ellisys Bluetooth Compliance Tester (Wednesday Jan. 03, 2018)
  CEVA today announced that it has completed qualification testing of its Bluetooth 5 Low Energy (LE) IP, including all the new optional Bluetooth 5 features using the recognized Ellisys Bluetooth Qualifier (EBQ™) Compliance Tester.
  
  
• eVaderis Completes Tape-Out of Innovative MRAM-Based, Memory-Centric MCU Demonstrator for Next-Generation IoT Applications (Tuesday Jan. 02, 2018)
  eVaderis, a semiconductor IP start-up that provides design solutions to improve the functionality, power efficiency and performance of its customers’ semiconductor chips, has successfully demonstrated a fully functioning design platform through an ultra-low-power microcontroller (MCU) in Beyond Semiconductor’s BA2X product line.
  
  
• Creonic Launches 5G Product Line with Polar and LDPC FEC IP Cores (Monday Dec. 18, 2017)
  Creonic GmbH today announced its new product line for 5G FEC (forward error correction). The product line covers LDPC decoder as well as Polar encoder and decoder IP cores for this latest 3GPP specification (3GPP Release 15).
  
  
• ICE-P3 EPU Upgrade Simplifies Control Of On-Chip And External Resources To Save More Power In SoC And MCU Designs (Thursday Dec. 14, 2017)
  Sonics upgraded its ICE-P3™ Energy Processing Unit (EPU), the flagship member of the ICE-Grain™ Family of EPU products, to add a new programmable Sequencer. The Sequencer enables designers of power-sensitive chips like systems-on-chip (SoC) and microcontrollers (MCU) to significantly improve control over both on-chip and external voltage and frequency resources to minimize energy consumption.
  
  
• Innovative Logic USB 3.1 Gen 2 IP got Certification from USB-IF (Wednesday Dec. 13, 2017)
  Inno-Logic’s USB3.1 gen2 device controller along with PHY from M31 Technology again successfully passed all compliance tests and received certification from USB-IF in November 2017. Besides USB 3.1 gen 2 Controller IP, the USB 2.0 device controller IP also passed the certification test in November, 2017.
  
  
• Performance-IP, CEVA Collaborate to Accelerate DSP System Performance (Tuesday Dec. 12, 2017)
  Performance-IP, the intellectual property (IP) leader in memory interfaces optimization, today announced a collaboration with CEVA to provide high-performance caching capabilities for CEVA’s digital signal processors (DSPs).
  
  
• Kilopass NVM OTP IP Achieves 3-Lot Qualification on GLOBALFOUNDRIES 14nm LPP (Low Power Process) Process Technology (Tuesday Dec. 12, 2017)
  Kilopass Technology Inc., a leading provider of semiconductor logic embedded non-volatile memory (eNVM) intellectual property (IP), today announced that it successfully achieved a three-lot qualification on GLOBALFOUNDRIES (GF) 14nm LPP (Low Power Process) technology platform for its one-time programmable (OTP) NVM technology.
  
  
• Digital Core Design introduces I3C IP Core (Tuesday Dec. 05, 2017)
  IP Core provider and System-on-Chip design house from Poland introduced the DI3CM-FIFO IP Core. It incorporates all features required by the latest MIPI I3C specification. Keeping the best assets from its elder brother, the I3C has major improvements in use and power and performance.
  
  
• Arasan Announces Industry's First MIPI C-PHY HDK (Tuesday Dec. 05, 2017)
  Arasan today announced availability of its MIPI C-PHY[SM] HDK built using an Arasan C-PHY ASIC. The HDK supports C-PHY v1.1 with speeds of up to 2.5 GHz and D-PHY v1.2 also with speeds of up to 2.5GHz.
  
  
• Synopsys Delivers a Complete HDMI 2.1 IP Solution with HDCP 2.2 Content Protection (Thursday Nov. 30, 2017)
  Synopsys, Inc. (Nasdaq:SNPS), today announced its complete DesignWare® HDMI 2.1 IP solution with High-Bandwidth Digital Content Protection (HDCP) 2.2 consisting of controllers, PHYs, verification IP, IP Prototyping Kit, and IP Subsystem as well as Linux software drivers.
  
  
• With its Modular Switch and End-System IP Technology combining both AFDX and PTP protocols SILKAN hits its target (Thursday Nov. 30, 2017)
  SILKAN Company, expert in real time solution known by its CetraC Modular IP technology developed according to DO-254 process, is proud to announce the successful wedding of the real-time and deterministic Ethernet with the IEEE-1588 protocol.
  
  
• Minima Processor Reduces SoC Energy Consumption for Near-Threshold Voltage Design (Tuesday Nov. 28, 2017)
  Minima Processor today announced its ultra-low power technology for near-threshold voltage design that uses its patented dynamic margining to minimize energy consumption while maintaining yield in systems-on-chip (SoCs).
  
  
• Codasip Announces Bk5-64, a New 64-bit RISC-V Processor (Tuesday Nov. 28, 2017)
  Codasip today announced that it has expanded its Berkelium processor portfolio to include the Bk5-64, its first implementation of the 64-bit RISC-V ISA.
  
  
• Titan IC launches "Hyperion F1 10G RegEx File Scan" on AWS Marketplace (Tuesday Nov. 28, 2017)
  Titan IC puts the power of the search in your hands with the most flexible, customisable regular expression processor running at lightning speeds available now on the Amazon EC2 F1 compute instance, which is a compute instance with field programmable gate arrays (FPGA), in the cloud.
  
  
• TTTech collaborates with Intel to develop FPGA-based TSN solution for Industrial Automation (Monday Nov. 27, 2017)
  TTTech is collaborating with Intel on the solution, which combines a high-performant Intel SoC FPGA platform with best-in-class TSN Ethernet IP from TTTech, along with embedded software and drivers.
  
  
• EnSilica's RADAR Imaging Co-processor addresses problem of automotive data overload to accelerate development of self-drive cars (Monday Nov. 27, 2017)
  EnSilica has announced a key innovation that will help the rapid development of autonomous cars. Its eSi-ADAS™ RADAR Imaging Co-processor will accelerate the commercialisation of autonomous vehicles by solving the current problem of RADAR data overload and resolution by handling this in a dedicated co-processor to enable tracking of potentially hundreds of objects to be made in real time.
  
  
• Dolphin Integration breakthrough innovation for TSMC 180 nm BCD Gen 2 process: Up to 30% savings in silicon area with the new SpRAM RHEA (Monday Nov. 27, 2017)
  Relying on robust, dense and low-power RAMs is pivotal for Fabless companies; the appraised single-port RAM RHEA compiler combines all three of these characteristics. Users of the TSMC 180 nm BCD Gen 2 process now benefit from the most competitive RAM.
  
  
• Digital Blocks DB9000 Display Controller & Processor IP Core Family Extends Leadership Across Medical, Industrial, Aerospace, Automotive, Communications, Computer, Monitor, Consumer, IoT, AR/VR Headsets, Wearables, Signage, and Cinema Applications (Monday Nov. 27, 2017)
  Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with display controller, 2D graphics, or video processing requirements, extends the leadership of the DB9000 Display Controller & Processor IP Core Family across a wide range of applications.
  
  
• Broadcom Announces Industry's First Silicon-Proven 7nm IP for ASICs in Deep Learning and Networking Applications (Tuesday Nov. 21, 2017)
  Broadcom today announced the industry’s first silicon-proven 7nm intellectual property (IP) for an ASIC platform targeting deep learning and networking applications.
  
  
• Barco Silex VC-2 HQ compression cores at the heart of IMAGENICS 4K HDMI-over-coax extender (Thursday Nov. 16, 2017)
  Barco Silex, the leading provider of IP cores for the audiovisual industry, announces that IMAGENICS, a major manufacturer of high-quality professional A/V products, has licensed its VC-2 HQ cores for video compression. The cores have been integrated in HDMI 2.0 transmitter and receiver modules and are instrumental in allowing the long-range transmission of 4K video over coax cabling with visually lossless quality and minimal latency.
  
  
• Enyx Premieres the First TCP and UDP Offload Engines for Intel Stratix 10 FPGA On REFLEX CES XpressGXS10-FH200G Board (Thursday Nov. 16, 2017)
  Enyx is pleased to announce its enterprise-class TCP/IP, UDP/IP and MAC network connectivity Intellectual Property (IP) Cores for FPGAs and SoCs support for the high-performance REFLEX CES XpressGXS10-FH200G PCIe Board, which features a Stratix 10 GX FPGA from Intel’s new top-of-the-line 14nm Stratix 10 family
  
  
• Faraday Unveils M1+ Library with Enhanced Routability on UMC 28HPC Process (Thursday Nov. 16, 2017)
  Faraday Technology today introduced its M1+ standard cell library on UMC 28HPC process. This optimized M1+ library supports the essential multi-track cells (7T/9T/12T), multi-Vt cells (LVT/RVT/HVT), and Faraday low-power PowerSlash™ kit to build the best portfolio of power, performance, and area metrics which are critical to optimizing digital design implementations targeted at diverse market applications.
  
  
• Global Unichip Successfully Tapes Out 16nm TCAM Compiler (Thursday Nov. 16, 2017)
  Global Unichip successfully taped its newest high speed TCAM compiler, specifically designed for high speed networking applications, that targets TSMC's 16FFC process technology. The company also said that it will conduct a similar tape out to TSMC's 7-nanometer process in March, 2018.
  
  
• Kilopass Achieves 1000-Hour Qualification on Mie Fujitsu Semiconductor Highly Demanded 40nm Low Power Process (Wednesday Nov. 15, 2017)
  Kilopass Technology today announced that it successfully achieved 1000-hour qualification and characterization on the 40nm Low Power Process of Mie Fujitsu Semiconductor, a Japan-based pure-play foundry company.
  
  
• Inside Secure Unveils Industry's First Root-of-Trust Solution based on RISC-V Processor (Wednesday Nov. 15, 2017)
  Inside Secure (Euronext Paris: INSD), at the heart of security solutions for mobile and connected devices, today announces the launch of its Silicon IP Programmable Root-of-Trust Engine, the industry’s first RISC-V -based platform security solution.