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IP / SOC Products News

• Enosemi announces availability of C-band-compatible electronic-photonic design IP (Tuesday Jun. 25, 2024)
  Enosemi announces the availability of C-band electronic-photonic design IP in the GlobalFoundries 45SPCLO Fotonix platform.
  
  
• SignatureIP Makes Network-on-Chip (NoC) Design Widely Accessible with Cloud-Based iNoCulator™ Platform (Monday Jun. 24, 2024)
  Available at iNoCulator.ai, it is the first cloud-based platform for design of a Network on Chip (NoC). A NoC provides the interconnect infrastructure between key compute, storage, memory and I/O blocks in a semiconductor chip.
  
  
• Baya Systems and Blue Cheetah Partner to Deliver Chiplet Interconnect Solutions (Monday Jun. 24, 2024)
  Integrating Baya Systems' WeaveIP™ NoC, and Blue Cheetah BlueLynx™ Die-to-Die (D2D) PHY IP solves many of the complexities of chiplet interconnect, greatly simplifying the architecture and design process for chiplet-based systems.
  
  
• Ceva Extends its Smart Edge IP Leadership, Adding New TinyML Optimized NPUs for AIoT Devices to Enable Edge AI Everywhere (Monday Jun. 24, 2024)
  Ceva today announced that it has extended its Ceva-NeuPro family of Edge AI NPUs with the introduction of Ceva-NeuPro-Nano NPUs.
  
  
• Baya Systems Introduces New Technology to Transform SoCs and Chiplets for Emerging Applications (Friday Jun. 21, 2024)
  Baya Systems today emerged from stealth mode to announce its software-driven IP technology portfolio designed to accelerate complex single-die and multi-die SoC designs.
  
  
• Alphawave Semi Unlocks 1.2 TBps Connectivity for High-Performance Compute and AI Infrastructure with 9.2 Gbps HBM3E Subsystem (Thursday Jun. 20, 2024)
  Robust, chiplet-enabled platform based on Micron HBM3E supports best-in-class performance and exceptional power efficiency
  
  
• System-level UCIe IP for early architecture analysis of 3D Chiplet Design and Packaging (Thursday Jun. 20, 2024)
  Mirabilis Design announced today the full support for System-level UCIe IP and a architecture exploration platform for early Chiplet package design for a range of applications in its flagship EDA tool VisualSim Architect.
  
  
• M31 Announces the Launch of Advanced LPDDR Memory IP to Support HPC Applications (Wednesday Jun. 19, 2024)
  M31 Technology announced the launch of the latest LPDDR memory IP solution to meet the growing demand in the high-performance computing (HPC) application market.
  
  
• Movellus Introduces Aeonic Power™ Product Family for On-Die Voltage Regulation (Wednesday Jun. 19, 2024)
  he Aeonic Power family debuts with two products: Aeonic Power™ HC, enabling energy optimization of digital cores and logic blocks, and Aeonic Power™ LN to simplify power delivery for die-to-die interfaces (e.g. UCIe).
  
  
• OPENEDGES to Premiere PHY Vision 2.0 at Design Automation Conference 2024 (Wednesday Jun. 19, 2024)
  OPENEDGES is thrilled to unveil the live demo of the 2.0 release of PHY Vision, an advanced LPDDR PHY visualization and exploration software, at the Design Automation Conference (DAC) 2024.
  
  
• Dream Chip and Cadence Demo Automotive SoC Featuring Tensilica AI IP at embedded world 2024 (Wednesday Jun. 19, 2024)
  Cadence and Dream Chip demonstrated Dream Chip’s latest automotive SoC, which features the Cadence® Tensilica® Vision P6 DSP IP and Cadence design IP controllers and was taped out using the complete Cadence® Verification solution and full-flow digital implementation, including signoff.
  
  
• Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for High-Performance Compute and AI Infrastructure (Thursday Jun. 13, 2024)
  Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure, today announced the successful tape-out of the industry’s first off-the-shelf multi-protocol I/O connectivity chiplet on TSMC’s 7nm process.
  
  
• Synopsys Achieves Certification of its AI-driven Digital and Analog Flows and IP on Samsung Advanced SF2 GAA Process (Thursday Jun. 13, 2024)
  Production-Ready Design Flows, Multi-Die Solution, and Synopsys IP Deliver a Proven Path to Unparalleled Power and Performance for AI and HPC Designs
  
  
• ADTechnology announces next-generation platform "ADP600" at Samsung Foundry Forum 2024 (Thursday Jun. 13, 2024)
  ADTechnology announces that they will be participating in the Samsung Foundry Forum (SFF) 2024 and Samsung Advanced Foundry Ecosystem (SAFE) Forum 2024 in San Jose, California, USA, on 12th-13th June (local time).
  
  
• Rambus Unveils PCIe 7.0 IP Portfolio for High-Performance Data Center and AI SoCs (Wednesday Jun. 12, 2024)
  The relentless innovation in Artificial Intelligence (AI) and High-Performance computing (HPC) demands a cutting-edge hardware infrastructure capable of handling unprecedented data loads.
  
  
• Alphawave Semi to Showcase Next-Generation PCIe® 7.0 IP Platform for High-Performance Connectivity and Compute at PCI-SIG® DevCon 2024 (Wednesday Jun. 12, 2024)
  The company will demonstrate IP subsystem solutions for rapid implementation of next-generation PCI Express® (PCIe®) 7.0® specification alongside advanced technologies that set new standards for the PCIe 6.0 technology ecosystem.
  
  
• Synopsys Accelerates Trillion Parameter HPC & AI Supercomputing Chip Designs with Industry's First PCIe 7.0 IP Solution (Monday Jun. 10, 2024)
  Synopsys, Inc. (Nasdaq: SNPS) today announced the industry's first complete PCIe 7.0 IP solution consisting of controller, IDE security module, PHY, and verification IP.
  
  
• OPENEDGES Announces Silicon-Proven Success of its LPDDR5X Combo PHY IP on Samsung Foundry's SF5A Technology (Monday Jun. 10, 2024)
  OPENEDGES Technology, Inc. (OPENEDGES), a leading provider of memory subsystem intellectual property (IP), is excited to announce the successful silicon bring-up of its LPDDR5X PHY IP on Samsung Foundry’s SF5A process technology.
  
  
• Mobiveil's PSRAM Controller IP Lets SoC Designers fully Leverage AP Memory's Ultra High Speed (UHS) PSRAM Memory (Friday Jun. 07, 2024)
  Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced it has adapted its PSRAM controller IP to leverage the unique characteristics of AP Memory’s Ultra High Speed (UHS) PSRAM device.
  
  
• Qualitas Semiconductor Announces 5nm MIPI C-PHY IP with 8Gsps Data Rate (Wednesday Jun. 05, 2024)
  QUALITAS SEMICONDUCTOR announces the successful development MIPI C-PHY TX/RX IP supporting a maximum data rate of 8.0Gsps and compliant with MIPI C-PHY Standard v2.1.
  
  
• Skymizer Launches Groundbreaking LLM Accelerator IP for on-device LLM Inferencing, EdgeThought, the game-changer in on-device GenAI era (Wednesday Jun. 05, 2024)
  Skymizer, a pioneer in compiler technology and optimized solutions, today announced the release of its revolutionary software-hardware co-design AI ASIC IP, EdgeThought, specifically engineered for accelerating Large Language Models (LLMs) at the edge.
  
  
• RaiderChip launches its Generative AI hardware accelerator for LLM models on low-cost FPGAs (Wednesday Jun. 05, 2024)
  The startup pioneers Edge Generative AI inference on small devices, thanks to the efficiency of its AI accelerator IP core: the GenAI v1
  
  
• Codasip introduces best-in-class RISC-V core for power-efficient applications (Tuesday Jun. 04, 2024)
  Codasip L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market
  
  
• New LZ4 & Snappy IP Core from CAST Enables Fast Lossless Data Decompression (Tuesday Jun. 04, 2024)
  The new LZ4SNP-D LZ4/Snappy Data Decompressor IP core receives compressed data files, detects the LZ4 or Snappy format, performs the appropriate decompression, and outputs the resulting uncompressed data.
  
  
• SureCore announces low power cryogenic memory technology that could help dramatically cut data centre power usage (Tuesday Jun. 04, 2024)
  One of the big challenges with data centres is amount of power that they consume. This is being further exacerbated by the increasing use of AI in the form of Large Language Models.
  
  
• Xiphera's Customisable nQrux™ Confidential Computing Engine Protects Cloud, Edge, and AI Environments (Thursday May. 30, 2024)
  nQrux™ CCE solution is customised to include various types of computing resources, while the communication of data and code is protected with hardware-based implementation of TLS 1.3.
  
  
• 4DS Unveils New Interface Switching ReRAM Technology for Faster and Energy Efficient Memory for AI Processing (Friday May. 24, 2024)
  4DS Memory Limited (ASX:4DS) today announced a new type of ReRAM technology for AI processing, bringing high-bandwidth, high-endurance persistent memory for big data and neural net applications.
  
  
• Qualitas Semiconductor's eDP RX PHY IP v1.5a is Ready for Mass Production (Thursday May. 23, 2024)
  Qualitas has expanded the IP portfolio on its silicon success with its eDP RX PHY line, specifically supporting eDP v1.5a, the latest specification.
  
  
• CFX announces commercial availability of low cost automotive grade SonoS based charge trapping EFlash/MTP technology on 90nm BCD process (Monday May. 20, 2024)
  Zhuhai Chuangfei Core Technology Co., Ltd. announced today that its latest developed high-reliability automotive-grade SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) EFlash/MTP technology based on the 90-nanometer BCD (Bipolar-CMOS-DMOS) process has officially entered commercial use.
  
  
• Digital Core Design in cooperation with DCD-SEMI Unveils DCAN-XL: Revolutionary CAN XL IP Core Bridging the Gap Between CAN FD and Ethernet (Tuesday May. 14, 2024)
  Designed to bridge the gap between CAN FD and 100Mbit Ethernet, the DCAN-XL sets a new standard in high-speed, reliable data transmission for automotive and industrial applications.