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IP / SOC Products News

• ARM and TSMC unveil roadmap for 64-bit ARM-based processors on 10FinFET process technology (Thursday Oct. 02, 2014)
  ARM® and TSMC today announced a new multi-year agreement that will deliver ARMv8-A processor IP optimised for TSMC 10FinFET process technology. Because of the success in scaling from 20SoC to 16FinFET, ARM and TSMC have decided to collaborate again for 10FinFET.
  
  
• New ARM Implementation Solutions Reduce Time to Market for FinFET Designs (Wednesday Oct. 01, 2014)
  ARM® today announced the introduction of two new physical IP implementation solutions for its silicon partners to help simplify the path to implementation for their FinFET physical designs. ARM Artisan® Power Grid Architect will reduce overall design time by creating optimal SoC power grid layouts while ARM Artisan Signoff Architect increases accuracy and precision in managing on-chip variation over existing methodologies.
  
  
• D68HC11K with applications notes, development board & tools from Digital Core Design (Wednesday Oct. 01, 2014)
  Digital Core Design has introduced the D68HC11K, which is a synthesizable soft IP Core Microcontroller, fully compatible with the Motorola MC68HC11K industry standard. It can be used as a direct replacement for the microcontrollers like: MC68HC11K0, MC68HC11K1, MC68HC11K4, MC68HC711K4, MC68HC11KS2 and MC68HC711KS2.
  
  
• Rambus Cryptography Research Division Launches Suite of DPA Resistant Cores Addressing the Continuing Rise in Data Theft (Wednesday Oct. 01, 2014)
  Rambus today announced that its Cryptography Research division has introduced a family of differential power analysis (DPA) resistant cryptographic cores. As part of Rambus’ overall IP cores program, these ready-to-use IP cores offer chipmakers an easy-to-integrate security solution with built-in side channel resistance for cryptographic functions across a wide range of connected devices.
  
  
• Arteris FlexNoC Resilience Package Enhances Redundancy, Fault Tolerance for Mission Critical Systems-on-Chip (Tuesday Sep. 30, 2014)
  Arteris today announced the new FlexNoC Resilience Package designed to increase reliability and lower the cost of developing resilient and fault tolerant systems-on-chip (SoCs). The FlexNoC Resilience Package enhances the benefits of Arteris FlexNoC network-on-chip fabric IP to automotive, aerospace defense, industrial equipment and other electronics markets requiring fault tolerance.
  
  
• TSMC and ARM set new benchmarks for performance and power efficiency with first announced FinFET silicon with 64-bit ARM big.LITTLE technology (Tuesday Sep. 30, 2014)
  TSMC and ARM® today announced the results from a key FinFET silicon validation of the ARM big.LITTLETM implementation, using ARM Cortex®-A57 and Cortex-A53 processors on TSMC’s advanced 16nm FinFET (16FF) process technology.
  
  
• Silicon-Proven Mixed Signal IP Products on 16nm FinFET (Tuesday Sep. 30, 2014)
  Analog Bits today disclosed working test-chips based upon their new Mixed Signal Design Kits on TSMC’s latest 16nm FinFET process.
  
  
• Cadence IP Portfolio and Tools to Support New TSMC Ultra-Low Power Technology Platform (Monday Sep. 29, 2014)
  Cadence today announced that the company is supporting TSMC’s new ultra-low power (ULP) technology platform with its extensive IP portfolio and suite of digital and custom/analog tools.
  
  
• Cadence Unveils Broad IP Portfolio for New TSMC 16nm FinFET Plus Process (Monday Sep. 29, 2014)
  Cadence today announced a broad portfolio of intellectual property (IP) for TSMC’s 16nm FinFET Plus (16FF+) process. Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the development of advanced SoC designs.
  
  
• Are you ready to conquer PCIe 4.0 challenge? PLDA is ready (Thursday Sep. 25, 2014)
  PLDA has optimized its ASIC intellectual property (IP) cores for the next generation of the ubiquitous and general purpose PCI Express® I/O specification, 4.0. PLDA’s proven 3.0 architecture enables easy migration to PCIe 4.0, with no interface changes necessary, and preserves existing behavior for seamless integration.
  
  
• GUC Rolls Out New Low Power Solid State Drive IP Portfolio (Thursday Sep. 25, 2014)
  Global Unichip today rolled out an expanded interconnect low power IP portfolio for ASICs targeting solid state drive (SSD) applications. The expansion covers ultra low power PCIe 3/4 PHY, DDR3/4, LPDDR3/4 CTRL/PHY and ONFi4.0 IO/PHY.
  
  
• ARM Supercharges MCU Market with High Performance Cortex-M7 Processor (Wednesday Sep. 24, 2014)
  ARM has unveiled a new 32-bit Cortex-M processor that delivers double the compute and digital signal processing (DSP) capability of today's most powerful ARM-based MCUs.
  
  
• Coreworks develops audio IP core for integration in SoC and FPGA for 8K UHDTV encoding (Tuesday Sep. 23, 2014)
  Coreworks together with its representative in Japan, Spinnaker Systems Inc., announce that Coreworks has now completed the development of an audio encoding system to support multiple audio formats and multiple audio streams for the next generation of UHDTV, known as 8K UHDTV.
  
  
• Broadcom Enables Industry's First 20 nm 100G Coherent PHY (Monday Sep. 22, 2014)
  Broadcom today announced that its high performance 20 nanometer (nm) signal processing enhanced mixed signal technologies has enabled NTT Electronics' new NLD0640 100G coherent digital signal processor (DSP) — an industry first.
  
  
• Synopsys' New DesignWare MIPI D-PHY Cuts Area and Power by 50 Percent (Wednesday Sep. 17, 2014)
  Synopsys today announced that it has cut the area and power consumption of its DesignWare® MIPI® D-PHY™ by 50 percent compared to competitive solutions while increasing performance to 2.5 Gbps per lane, reducing system-on-chip (SoC) silicon cost and extending battery life for mobile, consumer and automotive applications.
  
  
• Open-Silicon Speeds and Simplifies ASIC Development For 100G Networks (Tuesday Sep. 16, 2014)
  Open-Silicon today announced a 28Gbps Serializer/Deserializer (SerDes) evaluation platform for ASIC development that will enable the rapid deployment of chips and systems for 100G networks. The platform includes a full board with packaged 28nm test chip, software and characterization data.
  
  
• Semtech Provides Ultra-High Speed ADC and DAC for Advanced Digital Microwave Systems (Tuesday Sep. 16, 2014)
  Semtech today announced that 64GSPS ADC and DAC cores are available utilizing IBM's 32nm SOI technology for integration in high performance Digital Microwave System on Chip (SoC) solutions.
  
  
• MagnaChip to Offer 0.13um Embedded EEPROM IP (Monday Sep. 15, 2014)
  MagnaChip today announced that it has finished development of a proprietary 0.13um embedded EEPROM IP which is suited for use in non-volatile memory (NVM) solutions such as touch controller IC and microcontroller (MCU) applications.
  
  
• Allegro DVT showcases its HEVC/H.265 Video Encoder IP at IBC 2014. (Tuesday Sep. 09, 2014)
  At IBC 2014, Allegro DVT will perform a live demonstration of its HEVC/H.265 encoder IP core. The demonstration will be conducted on a prototyping platform, demonstrating the features and video quality of our HEVC/H.265 encoder IP.
  
  
• Credo Announces First 56G SerDes Technology Based on Conventional NRZ Modulation (Tuesday Sep. 09, 2014)
  Credo Semiconductor today announced the industry's first SerDes transceiver technology that can deliver speeds up to 57.5Gbps using NRZ signaling. Credo was able to clock its device at 57.5 Gbps, achieving 50 Gbps speeds across a channel with more than 30 dB loss at Nyquist frequency.
  
  
• Xilinx, Northwest Logic and Xylon Provide Low Cost FPGA-based MIPI Interfaces for Video Displays and Cameras (Monday Sep. 08, 2014)
  Xilinx and Northwest Logic and Xylon, Xilinx Premier Alliance Members, announce the availability of a low cost Xilinx FPGA-based MIPI interface IP that is optimized for cost sensitive video displays and cameras.
  
  
• Sidense Demonstrates Working One-Time Programmable (OTP) Bit Cells in TSMC 16nm FinFET Technology (Thursday Sep. 04, 2014)
  Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that it successfully demonstrated read and write capability for its 1T-OTP bit-cell architecture on test silicon fabricated in a 16nm CMOS FinFET process.
  
  
• Intilop Releases Altera's Stratix IV/V FPGA platform with their 16K Concurrent-TCP-Session Hardware Accelerator (Thursday Sep. 04, 2014)
  The Complete ‘Full TCP stack’ pre-ported and verified on Altera Stratix IV/V Platform with Intilop’s 6th generation industry leader, delivers ‘77 nanosecond TCP processing times and 97% TCP throughput. Network Hardened, most reliable, mature and most widely adapted worldwide over the last 5 years.
  
  
• Kilopass' XPM Antifuse Embedded Non-Volatile Memory IP Successfully Completes TSMC9000 Qualification for TSMC 55nm HV Process (Wednesday Sep. 03, 2014)
  Kilopass today announced successful TSMC9000 qualification of its XPM one-time programmable (OTP) antifuse eNVM IP core.
  
  
• 64-bit MIPS Warrior core will change the game for CPUs from mobile devices to datacenter servers (Tuesday Sep. 02, 2014)
  Imagination Technologies (IMG.L) announces the highly-efficient MIPS I-class I6400 CPU family, the first IP cores to combine a 64-bit architecture and hardware virtualization with scalable performance through multi-threading, multi-core and multi-cluster coherent processing.
  
  
• Andes Technology Unveils New Low-Power Platform IP Ideal for Internet-of-Things, Wearable Devices (Tuesday Sep. 02, 2014)
  Andes Technology, Asia’s first dedicated vendor of 32-bit CPU cores and associated System-on-Chip (SoC) platforms, unveiled a new low-power SoC subsystem for expanding Internet-of-Things (IoT) and wearable device markets.
  
  
• A rethought PIC IP Core - the DRPIC1655X (Monday Sep. 01, 2014)
  Digital Core Design celebrating in 2014 15th Anniversary, presents the DRPIC1655X IP Core, which is compatible with the industry standard PIC 16XXX, but… ensures 4 times faster architecture and 1 system clock instruction execution time.
  
  
• Rambus and Northwest Logic Certify Interoperability of DDR4/3 PHY and Controller (Tuesday Aug. 26, 2014)
  Rambus and Northwest Logic today announced they have validated interoperability of the Rambus R+™ DDR4/3 PHY with the Northwest Logic DDR4/3 SDRAM Controller Core. The combined solution provides customers with a differentiated memory subsystem that brings together the superior signal integrity offered by the Rambus R+ PHY along with the robust Northwest Logic controller core for a proven and easy-to-integrate solution.
  
  
• SiliconArts May Disrupt Mobile Graphics (Monday Aug. 25, 2014)
  Seemingly out of nowhere -- well, South Korea actually -- a four-year old startup recently burst on the scene with a ray-tracing chip, the RayCore.
  
  
• New standard cell and memory libraries at 28 nm from Dolphin Integration (Monday Aug. 25, 2014)
  Dolphin Integration are proud to announce the launch of a complete panoply of memories and standard cells at TSMC 28 nm HPM/HPC. In order to meet the requirements of ultra low-power and cost-sensitive applications in this process, their expertise in Power Management Networks was instrumental for this new panoply.