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IP / SOC Products News

• BittWare and PLDA Partner to Deliver 10G Low Latency TCP Offload, UDP and PCIe IP Cores on Altera Stratix-based Hardware (Friday Dec. 06, 2013)
  BittWare and PLDA announced today that they have entered into a global Value Added Reseller (VAR) agreement to combine PLDA’s IP cores including a 10G TCP/IP Offload Engine Hardware Stack (QuickTCP), 10G UDP Hardware Stack (QuickUDP) and PCI Express DMA core as part of an integrated solution on BittWare’s Stratix V embedded COTS hardware.
  
  
• Kilopass XPM Non Volatile Memory IP Validated on IBM 45nm SOI Process Successfully Passing JEDEC 47 Testing to Assure 10-Year Operating Life (Friday Dec. 06, 2013)
  Kilopass today announced that its anti-fuse XPM (eXtra Permanent Memory) NVM IP has been validated “Ready for IBM Technology” in the IBM 45nm SOI (Silicon on Insulator) process. By successfully completing JEDEC 47 standard qualification on the IBM 45nm SOI process with no failures, Kilopass XPM NVM IP assures system on chip (SoC) designers of at least 10 years of operating life.
  
  
• DCD's HDLC/SDLC controller aims telecommunication (Monday Dec. 02, 2013)
  Digital Core Design has introduced its latest soft IP Core, the DHDLC. It’s been designed to control HDLC/SDLC transmission frame and optimized for great variety of 8, 16 and 32-bit MCUs.
  
  
• Creonic Reinforces Activities in Satellite Communication with New IP Cores (Tuesday Nov. 26, 2013)
  Creonic, a leading and ISO 9001:2008 certified IP core provider for communications, announced today two new IP cores for satellite communication. The IP cores are a DVB-S2 demodulator as well as a DVB-CID (Carrier ID) modulator.
  
  
• MagnaChip and YMC to Offer 0.35um and 0.18um Embedded Multiple-Time Programmable (MTP) IP Solutions (Monday Nov. 25, 2013)
  MagnaChip today announced that it now offers 0.35um and 0.18um standard multiple-time programmable intellectual property (MTP-IP) devices jointly developed with Yield Microelectronics Corporation (YMC) of Taiwan.
  
  
• Synopsys New Ultra Low-Power Non-Volatile Memory IP Cuts Power by 90 Percent and Size in Half (Wednesday Nov. 20, 2013)
  Synopsys today announced the availability of its DesignWare® AEON® Multiple-Time Programmable (MTP) Ultra Low-Power (ULP) Non-Volatile Memory (NVM) IP, optimized for the stringent power and area requirements of wireless and RFID/NFC ICs.
  
  
• Altera Releases New 100G Ethernet and Interlaken IP Cores To Drive High-Capacity Transmission and Backhaul Applications (Tuesday Nov. 19, 2013)
  Altera today strengthened its intellectual property (IP) portfolio with the addition of four new best-in-class IP cores to the company’s MegaCore IP library. These new best-in-class IP cores include an ultra-high performance and ultra-low latency 100G Interlaken, 100G Ethernet, 40G Ethernet and 10G Ethernet IP.
  
  
• Imagination unveils industry's most scalable Image Signal Processing architecture (Monday Nov. 18, 2013)
  Imagination Technologies (IMG.L) announces a ground-breaking new camera Image Signal Processing (ISP) architecture codenamed ‘Raptor.’ Imagination designed the PowerVR Series2 ‘Raptor’ imaging pipeline architecture from the ground-up to be optimized for integration into next-generation System-on-Chips (SoCs) for a broad range of imaging and vision applications.
  
  
• Imagination announces world's first Wi-Fi, Bluetooth, FM combo IP (Monday Nov. 18, 2013)
  Imagination Technologies (IMG.L) announces the world’s first IP that combines Wi-Fi, Bluetooth 4.0 and FM receiver in one configurable solution.
  
  
• EnSilica launches Constant False Alarm Rate (CFAR) IP for automotive driver-assist applications (Monday Nov. 18, 2013)
  EnSilica has launched a Constant False Alarm Rate (CFAR) soft IP core for use in situational awareness radar sensors for automotive driver-assist applications. The hardware accelerated CFAR IP is matched to EnSilica’s pipelined FFT IP core and, operating on continuous data at one bin per clock cycle, the combination of cores delivers a substantially reduced data set for analysis by the processor.
  
  
• Digital Blocks Releases 2nd Gen UDP/IP Hardware Stack / UDP/IP Off-Load Engine (UOE) Targeting High-Frequency Trading Systems (Tuesday Nov. 12, 2013)
  Digital Blocks today releases 2nd Gen DB-UDP-IP-HFT IP Core, a UDP/IP Hardware Stack / UDP Off-Load Engine (UOE) targeting Altera Stratix V and Xilinx Virtex 7 FPGAs on leading-edge network adapter cards with one or more 10 / 40 GbE network links.
  
  
• MorethanIP and Nine Ways Announce AMBA DMA Solution for MorethanIP 10/100, Geth, 10Geth MAC and Switch Ethernet Cores (Tuesday Nov. 12, 2013)
  
  
  
• PLDA Announces QuickPCIe Lite IP, Enabling the Industry's First True "Plug and Play" PCIe IP Solution (Thursday Nov. 07, 2013)
  PLDA today announced QuickPCIe Lite IP for FPGA, offering the industry’s only solution for a plug and play PCIe experience. PLDA’s innovative QuickPCIe Lite product is designed to work directly “out of the box” and does not require a customer to manipulate PCIe concepts, whether at the hardware or software level.
  
  
• CMT Multiple Time Programming Solution Qualified in Silterra 110nm High Voltage Technology (Thursday Nov. 07, 2013)
  SilTerra and Chip Memory Technology, Inc, an innovative memory IP design house, jointly announced today the production release of Multiple-Time-Programming (MTP) embedded non-volatile memory solution in SilTerra’s advanced 110nm High Voltage technology.
  
  
• Vivante Vega IP Enables Full GPU Hardware Virtualization on Mobile and Home Entertainment Devices (Wednesday Nov. 06, 2013)
  Vivante today announced another breakthrough in its leading PPA (Power, Performance, and Area) Vega graphics product line. For the first time, full hardware-accelerated GPU virtualization (vGPU) will allow SoC manufacturers to support multiple operating systems (OS) on consumer and embedded platforms for use in mobile, home entertainment, and automotive products.
  
  
• Synopsys Announces DesignWare ARC HS Processors for Next-Generation Embedded Data and Signal Processing Systems (Tuesday Nov. 05, 2013)
  Synopsys today announced availability of the first products in the new DesignWare® ARC® HS Processor Family. The 32-bit ARC HS34 and HS36 processors are the highest performance ARC processor cores to date, delivering 1.9 DMIPS/MHz at speeds up to 2.2 GHz in typical 28-nanometer (nm) silicon.
  
  
• CAST Enters Graphics Acceleration IP Market with New Cores that Complement GPUs and System Processors (Tuesday Nov. 05, 2013)
  CAST is answering systems designers’ needs for faster graphics processing with the first of a new series of IP cores for graphics acceleration and display. Available immediately are a 2D/2.5D Graphics Accelerator and a Multilayer Display Controller, both sourced from new technology partner Think Silicon.
  
  
• Faraday Announces Its Silicon Proven & Seamless Integrated MIPI CSI-2, DSI Controller & PHY IPs (Tuesday Nov. 05, 2013)
  Faraday Technology today announced the availability of two integrated MIPI IP solutions, the Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) IP solutions in UMC’s 40nm LP and 55nm SP process technologies.
  
  
• Dolphin Integration PWM audio DAC at 55 nm densest ever for STB and wireless audio devices (Thursday Oct. 31, 2013)
  Dolphin Integration rolls out sDACa-MT1.01, an ultra dense Pulse Width Modulated DAC for audio applications embedding valuable features for easier SoC integration while supporting sound amplifiers with both analog and digital inputs.
  
  
• Programmable Interrupt Controller D8259 from Digital Core Design (Thursday Oct. 31, 2013)
  Digital Core Design introduced in its offer the D8259. DCD’s Programmable Interrupt Controller is fully compatible with the 82C59A device.
  
  
• ARM Announces Complete Suite of Graphics Processing Technology (Wednesday Oct. 30, 2013)
  ARM today unveiled new additions to its Mali™ GPU family, the industry’s most widely-licensed GPU IP, which scales the entire product stack from premium mobile devices to cost-optimized smartphones.
  
  
• Kilopass Embedded Non Volatile Memory IP Has Passed Rigorous JEDEC Qualification on GLOBALFOUNDRIES 40nm LP Process in Time for Customer Production (Wednesday Oct. 30, 2013)
  Kilopass announced that its entire product line of anti fuse one-time programmable (OTP) eNVM has completed 1000 hours of JEDEC standard reliability testing for GLOBALFOUNDRIES’ 40nm low power process technology.
  
  
• Renesas Electronics Releases HEVC/H.265 Video Codec Hardware IP as Part of Expansion of Licensing Business (Tuesday Oct. 29, 2013)
  Renesas Electronics today announced the development of video codec intellectual property (IP) technology supporting the latest video encoding standard, HEVC/H.265, which is expected to be adopted in a wide range of markets, including mobile devices, consumer devices, vehicle information systems, and industrial equipment.
  
  
• Moortec Semiconductor Announces Industry Leading, High Accuracy On-Chip Temperature Sensor Range for Advanced Nodes (Tuesday Oct. 29, 2013)
  Moortec announces its range of high accuracy on-chip temperature sensors for advanced CMOS technologies. This latest range extends Moortec's position as a leading provider of embedded thermal sensors to semiconductor customers worldwide.
  
  
• sureCore Tapes-out Low Power SRAM IP Demonstrator Chip (Monday Oct. 28, 2013)
  sureCore Ltd has announced that it has taped out its low power SRAM IP demonstrator chip in STMicroelectronics’ 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) process.
  
  
• Arasan Chip Systems Introduces First eMMC v5.0 I/O PADs & PHY IP using TSMC 28nmHPM Process (Monday Oct. 28, 2013)
  Arasan announced today the availability of the most complete solution for the latest eMMC standard: Embedded MultiMediaCard (eMMC), Electrical Standard (5.0). Arasan’s new eMMC v5.0 solution uses TSMC’s 28HPM process to address the need for applications requiring high speed as well as low leakage power.
  
  
• Reflex CES' Aurora-Like 64B/66B IP Core Enables Mixed Vendor FPGA Designs (Monday Oct. 28, 2013)
  Based on Altera FPGAs, the new IP core supports 64B/66B encoding and high-speed interfaces up to 14.4 Gbps, enabling interoperability between Xilinx and Altera FGPAs, with an effective bandwidth of up to 97%.
  
  
• Dolphin Integration announces even denser 6-Track standard cells to decrease power consumption at 180/130 nm (Friday Oct. 25, 2013)
  
  
  
• ARM Targets Automotive and Industrial Control Markets with New Architecture (Wednesday Oct. 23, 2013)
  ARM has disclosed technical details of its new ARMv8-R architecture for real-time embedded processors for use in automotive electronics and other integrated safety and control applications. The ARMv8-R architecture builds on the rich heritage of the 32-bit ARMv7-R architecture used for the company’s market-leading Cortex®-R series of real time processors and complements the ARMv8-A architecture announced in 2011.
  
  
• Synopsys Extends DesignWare IP Portfolio for Data Center SoCs with Enterprise 40G Ethernet Controller IP (Tuesday Oct. 22, 2013)
  Synopsys today announced the availability of the DesignWare Enterprise 40G Ethernet MAC and PCS Controller IP as part of Synopsys' complete Enterprise 40G IP solution.