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IP / SOC Products News

• Memoir Systems Introduces Renaissance for Datacom Memory IP Enabling Terabit Computing (Tuesday Oct. 22, 2013)
  Memoir Systems today announced the immediate availability of Renaissance for Datacom, a new family of multiport memory generators that enables SoC architects to push the performance envelope of their next generation multi-terabit networking products.
  
  
• SaberTek Announced the Availability of a Complete Family of Wi-Fi RF Intellectual Properties fully compliant with IEEE 802.11 a/b/g/n/ac Specifications (Monday Oct. 21, 2013)
  SaberTek announced the availability of a prolific library of IPs targeting Wi-Fi RF front ends fully compliant to the IEEE 802.11 a/b/g/n/ac standards. This family contains nearly 20 silicon-proven cores with varying degrees of functionality and complexity. They are implemented in several popular process nodes from TSMC.
  
  
• OmniPhy Introduces HDMI 2.0 TX/RX Controller+PHY IP, Driving 6 Gb/s Over Wirebond Packages (Monday Oct. 21, 2013)
  OmniPhy today announced that it's Video Display IP Group will ship a new Silicon Intellectual Property (SiIP) platform supporting HDMI 2.0 TX and RX standards up to 6 Gb/s for deployment in system-on-a-chip (SoC) solutions for the ultra-high-definition (UHD) market.
  
  
• Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm (Friday Oct. 18, 2013)
  Dolphin Integration announces the SESAME BIV standard cell library as a major innovation for ultra low leakage always-on logic block.
  
  
• IPextreme Brings New ColdFire V1 Platform to Market (Wednesday Oct. 16, 2013)
  IPextreme announced today the availability of the new ColdFire® V1 Platform based on technology used in Freescale® Semiconductor’s ColdFire®+ family of products.
  
  
• CEVA Introduces the CEVA-XC4500, the World's First Vector Floating-Point DSP for Wireless Infrastructure Solutions (Wednesday Oct. 16, 2013)
  CEVA today introduced the CEVA-XC4500 DSP - the world's first vector floating-point DSP specifically designed for advanced wireless infrastructure solutions.
  
  
• Synopsys Introduces DesignWare ARC EM SEP Processor for Safety-Compliant Automotive Systems (Tuesday Oct. 15, 2013)
  Synopsys today announced availability of the new DesignWare® ARC® EM SEP (Safety Enhancement Package) Processor core for automotive safety-compliant applications.
  
  
• Imagination reveals first MIPS "Warrior P-class" CPU core (Monday Oct. 14, 2013)
  The new MIPS P5600 core delivers industry-leading 32-bit performance together with class-leading low power characteristics in a silicon footprint up to 30% smaller than comparable CPU cores, making it ideal for a wide range of mobile, consumer and embedded applications.
  
  
• Shikino Initiative to Commence Licensing of New High-speed JPEG Codec IP to Obtain Ultra-high Definition Images (Friday Oct. 11, 2013)
  Shikino today announced that it has launched a new high-speed JPEG codec IP , "KJN-7EX_LSC", and commences sales today. As a new product from the "KJN series" with the world's top share in the still image compression/decompression technology, "KJN-7EX_LSC" equips with high bit depths (12-bit/10-bit) to obtain ultra-high definition images and the lossless processing function.
  
  
• Cadence Introduces New Family of Silicon-Proven High Performance Data Converter IP for Advanced 28nm Node (Thursday Oct. 10, 2013)
  These new products uniquely meet the needs of designers working with emerging high-speed protocols such as WiGig (802.11ad), which runs on a 60 GHz spectrum with potential data throughput up to 7Gbps, as well as LTE and LTE Advanced.
  
  
• Cadence Offers Industry’s First Licensable Audio DSP IP Supporting Dolby Digital Plus with DS1 (Thursday Oct. 10, 2013)
  Cadence today announced that its Tensilica® HiFi Audio/Voice DSP is the first intellectual property (IP) core to offer a certified decoder for Dolby® DS1 for Dolby Digital Plus™ audio streams.
  
  
• Cadence Offers Industry's First IP Core Solution Supporting DTS Neural Surround (Thursday Oct. 10, 2013)
  Partnered with the Cadence Tensilica HiFi Audio/Voice DSPs, DTS Neural Surround brings a home theater-like experience to automobiles and A/V receivers, significantly enhancing the sound quality of upmixing from compressed media types like MP3.
  
  
• CAST Introduces H.264 Video Over IP Subsystem to Simplify Video Streaming Product Development (Thursday Oct. 10, 2013)
  The new H264OIP-HDE Subsystem integrates three IP cores available from CAST: the H.264 High Profile Video Encoder (H264-HP-E) core for high-quality video compression, and the RTP and UDP/IP hardware stacks for encapsulating video for Internet Protocol transmission.
  
  
• Arasan Chip Systems Announces Industry First M-PHY 3.0 Total IP Solution (Monday Oct. 07, 2013)
  Arasan today announced the availability of the industry’s first MIPI® M-PHY® 3.0-compliant IP supporting multiple speed gears and a broad range of high-speed interfaces for mobile applications.
  
  
• Vivante Unveils Less than 1 mm2 OpenGL ES 2.0 GPU for Wearables and Internet of Things (IoT) Devices (Monday Oct. 07, 2013)
  Vivante Corporation today announced an area-optimized version of its GC series OpenGL 2.0 ES GPU cores for Wearable and other IoT devices.
  
  
• Digital Core Design Announces SPI master slave enhanced with detectors (Monday Oct. 07, 2013)
  The DSPI_FIFO is a fully configurable SPI master/slave device, which allows to configure polarity and phase of a serial clock signal SCK. DCD’s core enables microcontroller to communicate with serial peripheral de-vices, but also to communicate with an interprocessor in a multi-master system. It supports all the features of SPI and transmission/reception FIFOs, to significantly reduce the CPU time.
  
  
• Digital Blocks Announces the AMBA Multi-Channel DMA Controller IP Core (Friday Oct. 04, 2013)
  The Digital Blocks DB-DMAC-MC-AMBA IP Supports 1 – 32 independent data block / packet / stream transfers in parallel, providing low and high performance data transfer rates among AXI, AHB, APB interconnect memories and peripherals as well as high and low performance Peripherals with unique or custom interfaces.
  
  
• PLDA announces enhanced SR-IOV support in their XpressRICH3 PCI Express Gen3 IP Solution, providing up to 512 virtual functions on a single PCIe instance (Tuesday Oct. 01, 2013)
  PLDA announced enhanced support of SR-IOV (single root I/O virtualization) within their XpressRICH3 PCI Express Gen3 IP solution, enabling customers to deploy virtualized applications more quickly and efficiently directly from within the PCI Express interface.
  
  
• Andes Leads The Industry by Reducing Power Consumption for New Embedded Devices (Tuesday Oct. 01, 2013)
  Andes Technology today disclosed plans for a new class of ultra-low power processor core solutions. These products will incorporate a new technology called FlashFetch™ as well as other energy reducing innovations.
  
  
• Analog Bits Announces New Family of Secure IP Subsystems (Tuesday Oct. 01, 2013)
  Analog Bits today revealed a new family of semiconductor IP products to increase on-chip security. These products will reduce vulnerability to malicious attacks by incorporating crystal-less oscillator technology, on-die sensors, real-time loggers and other unique features.
  
  
• Altera Completes Latest Upgrade to IP Portfolio Targeting 28 nm Devices (Monday Sep. 30, 2013)
  Altera today announced it has completed the latest upgrade to its portfolio of IP cores targeting 28 nm FPGAs and SoCs.
  
  
• Silicon Vision partners with Mindtree for Bluetooth Low Energy intellectual property solution (Monday Sep. 30, 2013)
  Silicon Vision Technologies and Mindtree have partnered to bring to market a state-of-the-art, integrated RF-baseband-stack intellectual property (IP) solution for Bluetooth Low Energy (also known as Bluetooth Smart) technology.
  
  
• Intilop's enhanced Dual 10G NIC powered by their 76 ns TCP accelerator beats Solarflare 10G NIC delivering 4x higher throughput and 4x lower latency (Thursday Sep. 26, 2013)
  Intilop announced performance test results of their hyper performance FPGA-NIC system solutions using Altera's™ Stratix IV/V powered by their industry leading 5th Gen. SX-Series 10G Ultra-Low latency 76 ns TCP and UDP Offload Cores delivering sub-micro second wire-to-host memory total latency via PCI express interface.
  
  
• videantis announces low-delay H.264 High 4:4:4 Intra profile video codec IP core (Wednesday Sep. 25, 2013)
  videantis today announced a new video codec specifically optimized for automotive applications. The codec implements the H.264 High 4:4:4 Intra Profile, has very low encoding and decoding delay, and supports 8, 10 or 12-bit samples for higher-dynamic-range video.
  
  
• M31 Announces MIPI M-PHY Passes TSMC IP Validation Center Program (Tuesday Sep. 24, 2013)
  M31's MIPI M-PHY has completed IP system validation with TSMC's IP Validation Center Program. The TSMC IP Validation Center Program is an extension of TSMC9000, focusing on the auditing of IP designs via silicon test chips.
  
  
• New Xilinx OTN SmartCORE IP for High Capacity Combined Ethernet and 100G OTN Switching Platforms and Packet-Optical Transport Systems (Monday Sep. 23, 2013)
  Xilinx today announced new OTN SmartCORE™ IP for high capacity combined Ethernet and 100G OTN switching platforms and Packet-Optical Transport Systems (P-OTS).
  
  
• Arasan Chip Systems Announces Industry First Universal Flash Storage 2.0 Total IP Solution (Friday Sep. 20, 2013)
  Arasan announced today the availability of the industry first Universal Flash Storage (UFS) 2.0 Controller IP for mobile SoC and UFS device manufacturers with a MIPI M-PHY® HS Gear 3 physical interface running at 5.8 Gbps per lane and supporting up to 2 lanes.
  
  
• Synopsys Announces Immediate Availability of Broad Portfolio of Interface IP for TSMC's 20SoC Process (Thursday Sep. 19, 2013)
  Synopsys today announced the availability of a range of DesignWare Interface IP on TSMC's 20-nanometer (nm) system-on-chip (SoC) process.
  
  
• Vanguard Video Announces Multi-Platform Support for H.265/HEVC (Thursday Sep. 19, 2013)
  Vanguard Video announced H.265/HEVC codecs for a broad range of hardware and software platforms, including x86, ARM, OpenCL GPU, and FPGA IP Cores.
  
  
• Cadence Offers Secure Digital 4.0 Host Controller IP Core (Monday Sep. 16, 2013)
  Cadence today announced the immediate availability of its Secure Digital (SD) 4.0 Host Controller Intellectual Property (IP) core, which allows designers to achieve the maximum memory card access performance of up to 312MB/s – 3X the performance of the previous specification.