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IP / SOC Products News

• Vivante Intros Vega GPUs to Maximize OpenGL ES 3.0 Performance in Mass Market Android and Chrome Devices with Screens of Any Size (Thursday Sep. 12, 2013)
  Vivante today announced its new Vega IP product line that brings GPU performance, API completeness and silicon cost-savings to SOC manufacturers addressing the global market for high performance, battery-efficient mass market devices – from Wearables to Streaming TV Dongles to Tablets and Smartphones.
  
  
• Barco Silex releases Video over IP with JPEG 2000 Reference Design at IBC 2013 (Thursday Sep. 12, 2013)
  Following the announcement of a joint program with Xilinx® to ease the development of video over IP solutions with a comprehensive platform combining hardware-validated IP, reference designs and systems integration services, Barco Silex announced today at IBC the release of the “Multi-channel Video over IP with JPEG 2000” reference design
  
  
• Synopsys Demonstrates Industry's First SuperSpeed USB Inter-chip (SSIC) Interoperability (Wednesday Sep. 11, 2013)
  Synopsys today announced the industry's first SuperSpeed USB Inter-chip (SSIC) interoperability demonstration. The demonstration shows the successful interoperability between Synopsys' DesignWare® USB 3.0 IP for SSIC and Intel Corporation's SSIC development platform, and is on display at the Intel Developer Forum 2013.
  
  
• PLDA's XpressRICH3 PCI Express 3.0 IP Passes PCI-SIG PCIe 3.0 Compliance Testing (Wednesday Sep. 11, 2013)
  PLDA today announced that its XpressRICH3™ PCI Express® (PCIe®) 3.0 solution, passed all Gold and Interoperability tests performed by the PCI-SIG® committee during its most recent workshop in August 2013.
  
  
• OmniTek Introduces Enhanced OSVP Scalable Video Processor IP (Wednesday Sep. 11, 2013)
  OmniTek is showing the latest version of its OSVP Scalable Video Processor IP block at its booth in IBC 2013 (Hall 6.A18). The OSVP block is able to process up to eight individually-configured video channels, carrying out a user-defined sequence of video processing actions including chroma re-sampling, colour space conversion, de-interlacing, cropping, resizing and frame synchronisation.
  
  
• GDA Introduces SSIC (Super Speed Inter-chip) IP (Tuesday Sep. 10, 2013)
  GDA Technologies announced availability of USB 3.0 SSIC (Super speed Inter-chip controller) IP. SSIC is a scalable high speed protocol that uses existing USB software infrastructure and achieves low power by utilizing MIPI’s M-Phy physical layer.
  
  
• intoPIX delivers new JPEG2000 RAW FPGA IP-cores to compress Camera Bayer pattern-images (Tuesday Sep. 10, 2013)
  intoPIX introduces a new range of JPEG2000-RAW IP-cores for FPGA that manage HD, 4K or 8K Bayer image sensor output from 10 to 16-bit with an efficient raw Visually lossless compression at various frame rates.
  
  
• Synopsys Announces DesignWare STAR Hierarchical System to Accelerate Silicon Testing of SoCs (Monday Sep. 09, 2013)
  Synopsys today announced availability of its DesignWare® STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including analog/mixed-signal IP, digital logic blocks, memory and interface IP.
  
  
• Barco Silex releases Multi-Channel Ultra HDTV 8K JPEG 2000 encoder and decoder cores (Friday Sep. 06, 2013)
  Barco Silex announced today the release of a new range of single-chip, multi-channel 8K UHDTV JPEG 2000 cores. The cores have been implemented on the 28nm FPGA’s and SoC’s of Altera and Xilinx.
  
  
• Synopsys Launches DesignWare HDMI 2.0 TX/RX Controller and PHY IP for Ultra High-Definition Multimedia Experience (Thursday Sep. 05, 2013)
  Synopsys today launched its DesignWare ® HDMI 2.0 TX/RX IP solutions, including controller, PHY, and example Linux drivers to reduce designers' integration risk and time-to-market.
  
  
• DCD announces new release of its D26C92 UART IP Core (Wednesday Sep. 04, 2013)
  The D2692 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681. But on the contrary to it, DCD’s IP Core offers additional features and deeper FIFOs, like 8 character receiver, 8 character transmit FIFOs, watch dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts.
  
  
• Semtech-Snowbush IP Announces Support for Common Electrical Interface (CEI) 25G and 28G On New 28nm PHY IP Platform (Wednesday Sep. 04, 2013)
  Semtech today announced that its Snowbush IP group will ship a new Silicon Intellectual Property (SiIP) platform supporting Common Electrical Interface (CEI) standards up to 28 Gigabits per second (Gbps) for deployment in high data-rate chip-to-chip and chip-to-module applications.
  
  
• P-Product and ASOCS Offer Software-Defined Radio Solution for Node B Base Stations (Tuesday Sep. 03, 2013)
  P-Product and ASOCS today announced a partnership to develop an SDR-based solution for Node B 3G base stations for the mobile infrastructure market.
  
  
• AlpCode Introduces Family of Efficient Cryptographic Hash Cores (Thursday Aug. 29, 2013)
  AlpCode introduced the AlpCode SHA family, a range of efficient hardware implementations of the Secure Hash Standard (NIST FIPS 180-4) algorithms.
  
  
• TICO, the new disruptive light visually lossless compression technology will be officially released at IBC 2013 (Thursday Aug. 29, 2013)
  At IBC, intoPIX launches the new disruptive light visually lossless compression standard that will be known collectively as TICO (pronounced “Teeco”). Designed to have an extremely tiny footprint in FPGA/ASIC fabric, it is nevertheless also powerful in software applications for real-time operation.
  
  
• Dolphin Integration enriches its line of 80251 with a new DMA for high density and robustness (Friday Aug. 23, 2013)
  Dolphin Integration presents a new peripheral to extend its wide offer for 80251 and 8051 microcontroller. The FlipDMA is proposed with many features, while presenting a small area of 0.03 mm2 for 2 channels on TSMC 0.18 µm G
  
  
• Memoir Systems' Renaissance 10x Brings Ultra High Performance to Embedded Memories (Tuesday Aug. 20, 2013)
  Renaissance 10X can generate memories with various read/write combinations for up to ten non-blocking active ports to achieve up to 10 billion memory operations per second (MOPS) in a 28nm process.
  
  
• Mobiveil Announces the Availability of All Key IP Components and Subsystem for an Integrated NVM Express Based PCIe-SSD Solution (Tuesday Aug. 13, 2013)
  Mobiveil today announced the availability of all key IP components for an integrated NVM Express based Solid State Drive (SSD) solution.
  
  
• Proton Digital Systems Announces FlashPro Media Manager - Enabling Next Generation MLC and TLC Flash in Consumer, Client and Enterprise Applications (Monday Aug. 12, 2013)
  Proton’s FlashPro Media Manager is a Flash Reliability Solution that delivers industry-leading Flash endurance and retention through advanced LDPC error correction codes coupled with Statistical Digital Signal Processing (S-DSP) at the lowest power and smallest footprint.
  
  
• Chips&Media Introduces CODA7-L for Low-cost Smartphones (Monday Aug. 12, 2013)
  Chips&Media has introduced its new CODA7-L video codec IP core that is designed for low-cost smartphones and tablets. CODA7-L build on the existing CODA7 series platform that is originally an HD multi-codec IP capable of HD(720p) encoding and full HD(1080p) decoding, was designed for silicon cost sensitive and power-constrained low-cost applications.
  
  
• HDL Design House Introduces JESD204B PCS Rx IP Core (Thursday Aug. 08, 2013)
  HDL Design House has announced the availability of its JESD204B PCS Rx IP core (HIP610). The JESD204B interface defines high-speed serial interconnections and provides a method to connect one or multiple data converters to a digital signal processing device.
  
  
• eMemory's NeoEE Technology Advanced into BCD Process Platform, Augment P-Gamma Silicon Intellectual Property Product Range and Accelerate the Integration Power Management ICs (Tuesday Aug. 06, 2013)
  eMemory announced today that its multiple-times-programmable (MTP) NeoEE eNVM technology is now supported on the BCD (Bipolar-CMOS-DMOS) process platforms.
  
  
• Xilinx Real-Time Video Engine features OmniTek Multi-channel Video Processor IP and OmniTek Zynq-based Video Development Platform (Friday Aug. 02, 2013)
  The latest Real-Time Video Engine reference design to be released by Xilinx (RTVE 2.1) is based around video application design consultancy OmniTek’s OSVP scalable video processor IP block and their OZ745 video development platform, which is based around Xilinx’s Zynq™-7045 All-Programmable SoC.
  
  
• Logicircuit Offers Comprehensive Portfolio of DO-254 Certifiable IP (Thursday Aug. 01, 2013)
  Answering the call for improved productivity and reduced cost in the development of complex airborne electronic hardware, Logicircuit, Inc. announces an extensive, and growing, catalog of soft IP targeting DO-254 compliant designs.
  
  
• Digital Core Design Introduces 80390 CPU (Thursday Aug. 01, 2013)
  Digital Core Design has introduced the DP80390 soft IP Core, which is 100% binary compatible with 8051 and 80390 instruction sets.
  
  
• Chips&Media Delivers its First AVS+ Core to Address the Growing Digital Set-top box Market in China (Thursday Aug. 01, 2013)
  Chips&Media announced today that it has delivered its CODA966 and CODA988, the first AVS+ enabled cores to a couple of leading semiconductor companies.
  
  
• Sidense Announces SHF 1T-OTP Non-Volatile Memory IP for Advanced Process Chip Designs (Wednesday Jul. 31, 2013)
  Sidense today announced its SHF (Sidense Hiper Fuse) one-time programmable (OTP) memory for ICs developed in advanced process at 40nm, 28nm, 20nm and smaller geometries.
  
  
• Synopsys Launches Ultra-Low Power IP Subsystem for Sensors (Tuesday Jul. 30, 2013)
  The fully configurable subsystem consists of a DesignWare ARC® EM4 32-bit processor, digital interfaces, analog-to-digital data converters (ADCs), hardware accelerators, a comprehensive software library of DSP functions and software I/O drivers.
  
  
• Altera Delivers Fully Verified EtherCAT Protocol IP Free of Upfront Licensing Fees (Monday Jul. 29, 2013)
  Altera today announced the availability of a fully verified EtherCAT protocol IP for Altera FPGAs. This announcement is the latest offering from the collaboration between Altera, EtherCAT Technology Group (ETG) and Softing Industrial Automation GmbH.
  
  
• Algo-Logic Systems 3rd Generation TCP Endpoint Achieves Ultra-low-latency of 76-nanoseconds on Stratix V FPGA (Monday Jul. 29, 2013)
  The IP-Core enables FPGA-implemented logic to directly communicate over 10 Gigabit Ethernet networks with remote hardware or software devices and includes a robust hardware application programming interface that supports multiple real-world accelerated finance use cases.