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IP / SOC Products News
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Imagination's Design Optimisation Kits (DOKs) deliver substantial silicon PPA gains while reducing design cycle times (Wednesday Jul. 24, 2013)
Imagination Technologies announces it is launching new Design Optimisation Kits (DOKs) to provide customers with the flexibility to optimise for power, performance and area (PPA) in its GPUs, CPUs and other IP core families.
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CEVA Extends SATA/SAS Portfolio With SAS-3 IP (Tuesday Jul. 23, 2013)
CEVA today announced the availability of its 12Gbps Serial Attached SCSI (SAS-3) Controller IP for licensing. With advanced performance and reliability features, CEVA's SAS-3 IP can enable customers to design best-in-class next generation enterprise storage products in a timely and cost-effective manner.
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Allegro DVT improves its HEVC Decoder silicon IP with 10 bit support (Friday Jul. 19, 2013)
Requirement of TV broadcasting for carrying 4K and ultra-high definition content is now driving the adoption of the HEVC (High Efficiency Video Coding) standard. This demand for devices supporting HEVC is growing fast, and Allegro DVT is ready with the industry’s first fully compliant HEVC decoding IP that supports both Main and Main10 profiles.
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Intilop delivers their enhanced Dual 10G iNICs with Ultra-low latency TCP and UDP Offload accelerators, benchmarking sub micro second wire-to-host latency and Ultra high data throughput (Thursday Jul. 18, 2013)
Intilop announced delivery of their hyper performance FPGA-NIC system solutions using Altera's Stratix IV/V powered by their industry leading 5th Gen.
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Semtech Announces a New PHY IP Platform from its Snowbush IP Group that Supports JESD204B, CPRI and OBSAI (Thursday Jul. 18, 2013)
Semtech today announced the availability of a multi-standard silicon IP (SiIP) PHY that supports the latest new standards for high-speed wireline and wireless networks.
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New low-power unified computer vision and video processing solution from videantis (Thursday Jul. 18, 2013)
The videantis processor is 100 times more powerful and consumes 1000 times less energy than host CPUs on video and vision applications
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Synopsys Announces Availability of Complete 28-nm Data Converter IP Portfolio (Wednesday Jul. 17, 2013)
Synopsys today announced the availability of its 28-nm data converter IP portfolio,which includes DesignWare® analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and integrated PLLs.
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Noesis Technologies Announces Availability of CVSD Voice Codec (Wednesday Jul. 17, 2013)
Noesis Technologies announced today the immediate availability of its CVSD voice codec algorithm compliant IP Core.
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Complete FPGA-Based MIPI Video Demonstration System Now Available (Tuesday Jul. 09, 2013)
Altima Corporation, Northwest Logic, and Meticom announce the immediate availability of a complete MIPI video demonstration system using Altera’s Cyclone IV and V FPGAs. This demonstration system takes an HDMI video stream, processes it in an Altera FPGA and then streams it to a MIPI-compatible display.
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Sydaap develops World’s First 64 Bit Floating Point FFT/IFFT Hardware Accelerator for N = 4096 (Monday Jul. 08, 2013)
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VeriSilicon Introduces Hantro G2 Video Decoder IP with HEVC and VP9 Support (Monday Jul. 01, 2013)
VeriSilicon announced today the availability of Hantro G2 multi-format video decoder IP to support ultra HD 4K video decoding for HEVC (High Efficiency Video Coding, aka H.265) video coding standard.
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Sital Integrates Wiring Testing Capabilities into Mil-Std-1553 IP Cores and Boards (Monday Jul. 01, 2013)
Sital Technology Ltd. announced today that its patented technology for detecting wiring faults will be integrated into its Mil-Std-1553 IP cores and boards.
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DCD Introduces Customizable LCD Controller (Thursday Jun. 27, 2013)
Digital Core Design has introduced a proprietary LCD controller equipped with 24-bit RGB output and synchronization. Moreover, like all DCD’s cores, the DLCD is provided as a fully synthesizable RTL therefore can be implemented in both ASICs/SoCs and FPGAs.
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Innovative Logic announced licensing of their USB 3.0 SuperSpeed OTG IP (Thursday Jun. 27, 2013)
Inno-Logic announced today the release of their USB3.0 OTG controller IP. Innovative Logic is the first company to announce the release of USB3.0 OTG controller IP.
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Imagination reveals key elements of its new MIPS CPU roadmap (Wednesday Jun. 26, 2013)
Imagination has updated its current portfolio of MIPS Aptiv cores, extending each of the Aptiv families with new core configurations. In addition, later this year Imagination will start rolling out an entire generation of new MIPS CPUs, including 32-bit and 64-bit cores.
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New Cadence Energy-Efficient PCI Express IP Helps Reduce Power Consumption for Datacenter and Enterprise Applications (Wednesday Jun. 26, 2013)
Addressing the design challenge of reducing energy consumption of power-hungry datacenters and enterprise applications, Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced new design IP for low-power PCI Express (PCIe®) development.
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Synopsys Demonstrates Industry's First M-PCIe IP Interoperability (Tuesday Jun. 25, 2013)
Synopsys today announced the industry's first M-PCIe interoperability demonstration. The demonstration shows the successful interoperability between M-PCIe interfaces from Synopsys and Intel using M-PCIe-based switch and endpoint devices.
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Chips&Media Unveils Breakthrough in Bandwidth Reduction (Monday Jun. 24, 2013)
Chips&Media has unveiled its innovative bandwidth saving technology to deliver premium 4K video content with merely a half memory bandwidth.
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Availability of Dolphin Integration's TSMC-sponsored ROM at the 130 nm BCD 5 V process (Friday Jun. 21, 2013)
Dolphin Integration today announces the availability of the silicon proven CASSIOPEIA generator for metal programmable ROM, at the TSMC 130 BCD 5V process.
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Multimedia IP leader Imagination Technologies enters the HEVC arena with a focus on image quality and multi-standard capability (Thursday Jun. 20, 2013)
Imagination Technologies announces that it is driving adoption of the HEVC (High Efficiency Video Coding) standard with its PowerVR Series5 HEVC-enabled encoder and decoder families.
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VeriSilicon Introduces Hantro G2 Video Decoder IP with HEVC and VP9 Support (Tuesday Jun. 18, 2013)
VeriSilicon announced today the availability of Hantro G2 multi-format video decoder IP to support ultra HD 4K video decoding for HEVC (High Efficiency Video Coding, aka H.265) video coding standard. The G2 IP also adds support for the upcoming VP9 web video format from the WebM Project.
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Mixel and GDA Technologies Partner to Deliver a Complete UFS MIPI Solution (Monday Jun. 17, 2013)
GDA Technologies and Mixel today announced the availability of a complete solution for the Mobile Industry Processor Interface (MIPI®) supporting M-PHY Universal Flash Storage (UFS) use-case. This joint solution consists of the Mixel MIPI M-PHY (Physical Layer) and the GDA MIPI UniproSM and UFS Cores delivered as silicon Intellectual Property (IP).
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Imec and Renesas Electronics Pioneer High-Performance RF Solutions in 28nm CMOS Technology (Monday Jun. 17, 2013)
imec and Renesas Electronics unveiled the world’s first multi-standard radio frequency (RF) receiver in 28nm CMOS technology, and a 28nm analog-to-digital converter (ADC) targeting wide-bandwidth standards such as LTE-advanced and next-generation WiFi.
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With BassPower for headphones, Dolphin Integration eliminates up to 80% of external capacitor cost (Friday Jun. 14, 2013)
Dolphin Integration blows it all by providing Audio Codecs with their new BassPower headphone feature. This innovation has been implemented in response to economical market constraints, thanks to its very low silicon area enabling a significant cost reduction of the Bill of Material.
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Arasan Chip Systems introduces USB 3.0 SSIC Bridge IP (Wednesday Jun. 12, 2013)
Arasan announced today the release of its SSIC Adapter IP, supporting the USB 3.0 specification for USB Superspeed Inter-Chip (SSIC).
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Synopsys Announces Design Kit Optimized for All SoC Processor Cores (Wednesday Jun. 12, 2013)
Synopsys today announced an extension to its DesignWare® Duet Embedded Memory and Logic Library IP portfolio specifically designed to enable the optimized implementation of a broad range of processor cores.
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Industry's First Secure Clock IP Core (Friday Jun. 07, 2013)
Analog Bits today disclosed a new family of ultra-secure clocking macros. These low-power IP cores are designed to increase a chipfs resistance to hacking and malicious attack without decreasing battery life or increasing heat.
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Northwest Logic's PCI Express 3.0 Solution passes PCI-SIG PCIe 3.0 Compliance Testing at First Official PCIe 3.0 Compliance Workshop (Wednesday Jun. 05, 2013)
Northwest Logic today announced that its PCI Express® (PCIe®) 3.0 solution, including the Expresso 3.0 Core (PCI Express 3.0 Controller Core) and Expresso DMA Core passed all Gold and Interoperability tests at the April 2013 PCI-SIG® Compliance Workshop. This testing was done with 8 lanes running at 8 Gbit/s SERDES rates at the first official PCIe 3.0 compliance workshop.
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Moortec Semiconductor Announces its Embedded Voltage Monitor IP on 28nm (Monday Jun. 03, 2013)
Moortec announces the Embedded Voltage Monitor (MEVM) IP on 28-nanometer (nm) and 65-nm low-geometry CMOS technologies. The MEVM IP allows developers of large scale semiconductor devices to monitor up to nine digital supply domains dynamically on-chip, optimising system performance, allowing Dynamic Voltage Scaling (DVS) and enhancing the design flow of System on Chip (SoC) developments.
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True Circuits Introduces a Revolutionary New DDR 4/3 PHY (Monday Jun. 03, 2013)
True Circuits announced today the introduction of a new high performance DDR 4/3 PHY with state-of-the-art tuning and training, and remarkable physical flexibility to adapt to each customer's die floorplan and package. The DDR 4/3 PHY has been developed using the powerful custom design automation tools that have made TCI's line of high performance PLLs and DLLs a staple in the semiconductor industry for over 15 years.








