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IP / SOC Products News

• Microsemi Achieves NIST Certification on EnforcIT Cryptography IP Cores for FPGA and ASIC Designs (Friday Apr. 12, 2013)
  Microsemi announced it has achieved National Institute of Standards and Technology (NIST) algorithmic certification on its U.S.-developed EnforcIT™ Cryptography Suite of National Security Agency (NSA) Suite B algorithms.
  
  
• ARM Announces POP IP for Cortex-A50 Series Processors on TSMC 28nm HPM and 16nm FinFET Processes (Tuesday Apr. 09, 2013)
  ARM today announced the availability of POP IP products for its ARMv8 architecture-based Cortex-A57 and Cortex-A53 processors for TSMC 28HPM process technology, as well as the roadmap for POP IP to TSMC’s 16nm FinFET process technology.
  
  
• intoPIX Launches New Ultra Compact JPEG2000 FPGA IP-cores at NAB2013 (Monday Apr. 08, 2013)
  intoPIX launches its customizable reference applications for JPEG 2000 targeting the smallest 28nm FPGA devices from Altera and Xilinx at NAB 2013.
  
  
• Brite's USB 2.0 OTG PHY Implementation Using SMIC 0.11um Process Receives USB-IF Certification (Monday Apr. 08, 2013)
  Brite Semiconductor today announced that its USB 2.0 physical layer (PHY) implementation, using SMIC 0.11um process, has passed USB-IF certification for Hi-Speed products. This newly implemented PHY is fully compliant with on-the-go (OTG) specification for both device and host applications.
  
  
• DI2CMS, I2C Master - Slave Bus Interface from Digital Core Design (Tuesday Apr. 02, 2013)
  Digital Core Design has introduced its newest I2C Bus Interface soft core. It is fully compatible with Philips v. 3.0 specification, which means, it can operate at Standard, Fast, Fast Plus and High Speed (up to 3,4 Mb/s).
  
  
• ARM and TSMC Tape-Out First ARM Cortex-A57 Processor on TSMC's 16nm FinFET Technology (Tuesday Apr. 02, 2013)
  ARM and TSMC today announced the first tape-out of an ARM® Cortex™-A57 processor on FinFET process technology. The Cortex-A57 processor is ARM’s highest performing processor.
  
  
• Sidense 1T-OTP NVM Qualified for 150 Degrees C Automotive High-Reliability Requirements on TSMC's BCD Process (Monday Apr. 01, 2013)
  Sidense announced today that the Company’s 1T-OTP macros for TSMC’s 180nm BCD 1.8/5V/HV and G 1.8/5V processes have met all of TSMC’s IP9000 Assessment program requirements.
  
  
• Sidense Qualifies 1T-OTP Non-Volatile Memory for MagnaChip 180nm Mixed-Signal and HV CMOS Process (Monday Mar. 25, 2013)
  MagnaChip and Sidense today announced that Sidense’s SLP 1T-OTP macros have been fully qualified for MagnaChip’s 180nm 1.8/3.3/18V high-voltage CMOS and mixed-signal process.
  
  
• MorethanIP Releases the Industry First IP for 100GBase-CR4 and 100GBase-KR4 Applications (Thursday Mar. 21, 2013)
  MorethanIP today announced the immediate availability of the industry first IP (Intellectual Property) solution for 100GBase-CR4 and 100GBase-KR4. The Core is compliant with the IEEE802.3bj latest Draft 1.3 specification and is optimized for ASIC technologies.
  
  
• GUC Unveils New 28nm Data Converter IP Family (Tuesday Mar. 19, 2013)
  Global Unichip Corp. (GUC) today announced a new family of silicon proven digital-to-analog converter (DAC) and analog-to-digital converters (ADC) IP targeting TSMC's 28nmHPM process technology.
  
  
• Chips&Media Extends CODA9 Series With AVS+ Chinese New Video Standard (Monday Mar. 18, 2013)
  Chips&Media today unveils the latest addition to its comprehensive multi-codec CODA9 family, the CODA966 video codec IP, including support for Chinese new AVS+ video standards.
  
  
• Andes Technology to Bring Energy Efficient Processor Cores to the U.S. Market (Thursday Mar. 14, 2013)
  Taiwan’s Andes Technology will extend support for its processor cores to U.S. semiconductor companies. The move marks a significant acceleration of business plans for the company at a time of consolidation in the processor core sector.
  
  
• HDL Design House Announces PCS IP Core (Tuesday Mar. 12, 2013)
  HDL Design House has announced availability of its Physical Coding Sublayer (PCS) IP core (HIP 500) which enables transmission and reception of data via 8-Lanes SerDes interface.
  
  
• Digital Core Design Announces DuART, tiny UART IP Core (Friday Mar. 08, 2013)
  DμART, the newest IP Core mastered by Digital Core Design, is one of the tiniest UART IP Cores available on the market. Small is beautiful, that’s why DCD’s tiny works not only in UART mode, but also implements separate BAUD clock line, false start bit detection, status report and internal diagnostic capabilities.
  
  
• Moortec Semiconductor Announce Technology for Robust 4G LTE Mobile Communications (Thursday Mar. 07, 2013)
  Moortec announces it's intention to transform the robustness of mobile communications with its novel signal processing receiver architecture. The technology targets the creators of 3G and 4G receive-chain solutions for mobile devices and supports WCDMA, LTE (FDD and TDD) and TDSCMDA standards.
  
  
• Renesas Electronics Develops and Supplies Multi-Format Video Codec Hardware IP that Supports Low-Delay Processing (Thursday Mar. 07, 2013)
  Renesas Electronics has developed and will start supply of a multi-format video codec hardware IP product that supports low-delay processing for automotive information terminals that support High Definition Television (HDTV), mobile devices such as smartphones and tablets, and industrial equipment.
  
  
• Dolphin Integration announces the availability of the new generation of Foundry Sponsored SpRAM generator at 55 nm (Monday Mar. 04, 2013)
  Dolphin Integration invites users of the TSMC 55 LP process to try out the latest Foundry Sponsored SpRAM released, known as SpRAM RHEA generator. This SpRAM is designed to reach the highest density and gains from 7% to 20% versus alternative solutions, depending on the memory configuration required.
  
  
• Arasan Announces eMMC 5.0 Total IP Solution at Mobile World Congress (Thursday Feb. 28, 2013)
  Arasan announced today support for the upcoming eMMC 5.0 specification which is proceeding to ratification within the JEDEC standards organization. The eMMC Total IP Solution comprises digital and analog IP cores, software stack, firmware and a hardware validation platform.
  
  
• VLSI Plus offers Multiple Video Source MIPI CSI2 Transmitter IP core (Wednesday Feb. 27, 2013)
  VLSI Plus today announced at the MWC conference the availability of the SVT-CS4-AP2 – a MIPI® CSI2 compliant serial video transmitter, supporting multiple concurrent video sources, and employing from 1 to 4 DPHY lanes at up to 1.5Gbps per lane.
  
  
• Rambus Unveils Binary Pixel Technology that Dramatically Improves Photo Quality in Mobile Devices (Monday Feb. 25, 2013)
  The Rambus binary pixel technlogy includes image sensor and image processing architectures with single-shot high dynamic range (HDR) and improved low-light sensitivity for better videos and photos in any lighting condition.
  
  
• Imec and Target present multi-standard low-power LDPC engine for multi-Gbps wireless communication (Monday Feb. 25, 2013)
  imec and Target Compiler Technologies announced that they extend their strategic collaboration on ASIP (application-specific instruction-set processor) designs in the field of mobile communication. One of the achievements endorsing their fruitful collaboration in the past years is a new multi-standard LDPC (low-density parity check) FEC (forward error correction) ASIP architecture template for multi-Gbps wireless communication.
  
  
• PowerVR G6100 Series6 "Rogue" core enables mass-market OpenGL ES3.0 (Monday Feb. 25, 2013)
  Imagination Technologies today announces the smallest area member of the ground-breaking PowerVR Series6 ‘Rogue’ family, which will enable mass-market adoption of OpenGL ES 3.0.
  
  
• LTE and LTE advanced baseband processing get performance boost from MIPS multi-threaded cores (Monday Feb. 25, 2013)
  Imagination Technologies announces that its multi-threaded MIPS® processor cores show significant performance benefits compared to single-threaded platforms for LTE baseband processing in user equipment (UE) such as mobile handsets and tablets.
  
  
• IDT Announces Data Compression IP Offering Industry's Highest Performance for 3G and 4G Wireless Infrastructure Applications (Thursday Feb. 21, 2013)
  IDT today announced data compression intellectual property (IP) that offers the industry’s highest performance in 3G and 4G wireless infrastructure applications. IDT’s patent-protected baseband data compression IP reduces system cost by enabling the use of low cost fiber optic cabling to connect the remote radio unit (RRU) to the baseband unit (BBU).
  
  
• Ultra-low power processor operates at near-threshold voltage (Thursday Feb. 21, 2013)
  At this week’s International Solid State Circuits Conference (ISSCC 2013), imec and Holst Centre presented an ultra-low power processor that operates reliably at near-threshold voltages. The processor delivers clock speeds up to 1MHz at voltages down to 0.4 V. In tests based on a Fast Fourier Transform use case, it consumed only 79 µW – a fraction of the power consumption at standard voltages.
  
  
• 1.9nJ/b Ultra-low power 2.4GHz multi-standard radio compliant to Bluetooth Low Energy and ZigBee (Thursday Feb. 21, 2013)
  Imec and Holst Centre presented at ISSCC an ultra-low power multi-standard 2.3/2.4GHz short range radio. The 1.9nJ/b radio is compliant with three wireless standards: Bluetooth ® Low Energy (BLE), ZigBee (IEEE802.15.4) and Medical Body Area Networks (MBAN, IEEE802.15.6).
  
  
• Xilinx Launches Fully Adaptive Gbps Class Point-to-Point Microwave Modem IP for Backhaul Applications (Wednesday Feb. 20, 2013)
  Xilinx announced today the availability of its new Gigabit class 1024QAM point-to-point (PtP) microwave modem IP for backhaul applications.
  
  
• Imagination achieves OpenGL ES 3.0 conformance for PowerVR Series6 cores (Wednesday Feb. 20, 2013)
  Imagination Technologies announces that its PowerVR Series6 ‘Rogue’ GPU (graphics processing unit) technology has been among the first to pass OpenGL ES 3.0 conformance with Khronos.
  
  
• CEVA Introduces MUST Multi-core System Technology, Adds Vector Floating-point Capabilities for CEVA-XC DSP Architecture Framework (Tuesday Feb. 19, 2013)
  CEVA today announced a suite of advanced processor and multi-core technologies to further enhance the CEVA-XC DSP architecture framework for high performance wireless applications including wireless terminals, small cells, access points, metro and macro base-stations.
  
  
• CAST Adds Multicast and AXI to UDP/IP Core for Streaming Media Systems (Tuesday Feb. 19, 2013)
  CAST has improved its UDP/IP Hardware Stack IP core with customer-requested features that make it even more effective for processor-less streaming of audio or video over Ethernet