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IP / SOC Products News
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S3 Group Launches 10 new Silicon Proven IP Cores (Monday Feb. 18, 2013)
S3 Group today announced the immediate availability of a number of new Mixed-Signal IP cores which have been developed and silicon proven during 2012.
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Vitesse Introduces IP Cores for Consumer, Enterprise and Industrial Applications (Monday Feb. 18, 2013)
Leading Gigabit Ethernet Switch Developer Licensing IP Cores with Timing Synchronization, Energy Efficient Ethernet and Audio Video Bridging.
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Creonic Announces WiGig (802.11ad) LDPC Decoder IP and Closes License Deal with Blu Wireless Technology (Monday Feb. 18, 2013)
Creonic today announced that it closed a license deal with Blu Wireless Technology Ltd. Creonic has licensed its new forward error correction LDPC decoder IP core designed to address the WiGig 60 GHz standard (IEEE 802.11ad) to Blu Wireless Technology - a System IP company developing configurable, low power and cost 60 GHz technology for the WiGig and Wireless Backhaul markets.
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Bwave and Ubiso to Demonstrate World's First Licensable Multi-Standard DVB-T2 DTV Demodulation IP Subsystem Based on Tensilica's ConnX BBE16 DSP (Friday Feb. 15, 2013)
Bwave’s engineers defined the system architecture and implemented the subsystem using Tensilica’s ConnX BBE16 DSP and Ubiso’s programmable DVB-x2 forward error correction (FEC) IP. This is a complete reference design platform, ready for chipmakers to drop into their DTV chip designs.
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RFEL Launches a Video Image Stabilisation IP Core (Thursday Feb. 14, 2013)
RFEL now has available its Video Image Stabilisation IP Core, which is the first of its recently announced family of Video Processing IP cores that fully utilises the power of the Xilinx Zynq-7000 All Programmable SoCs.
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Tensilica Unveils IVP - A New Imaging/Video DSP IP Core for Mobile Handsets, DTV, Automotive and Computer Vision Applications (Tuesday Feb. 12, 2013)
Tensilica, Inc. today introduced IVP, an imaging and video dataplane processor (DPU) that is ideal for the complex image/video signal processing functions in mobile handsets, tablets, digital televisiosn (DTV), automotive, video games and computer vision based applications.
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Dolphin Integration launches the kit of cells to build islets of the second generation (Friday Feb. 08, 2013)
Dolphin Integration is releasing SESAME CLICK, a kit of cells enabling the construction and integration of islets. Its low power cells optimized for TSMC 65 nm and 55 nm processes is enriched with a patented Transition Ramp Cell for an easy and safe construction of low energy circuits.
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Athena Announces Fastest Public Key Accelerator Core (Wednesday Feb. 06, 2013)
The Athena Group today announced the industry’s fastest public key (PK) accelerator core. The T6421 employs Athena’s patented arithmetic technology and patented cryptographic architecture to deliver extraordinary throughput across the entire spectrum of PK operations, and is specifically optimized for RSA-2048.
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GLOBALFOUNDRIES Details 14nm-XM FinFET Technology Performance, Power and Area Efficiency with a Dual-core Cortex-A9 Processor Implementation (Tuesday Feb. 05, 2013)
Based on the industry standard design implementation flows and sign-off simulations using real process data, GLOBALFOUNDRIES expects that a dual-core ARM Cortex-A9 processor manufactured on GLOBALFOUNDRIES’ 14nm-XM technology will deliver more than twice the energy efficiency of a similar 28nm-SLP technology based design, while requiring only half the chip area.
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GLOBALFOUNDRIES and Rambus Collaborate To Develop Broad IP Portfolio for 14nm-XM FinFET Process Technology (Tuesday Feb. 05, 2013)
GLOBALFOUNDRIES and Rambus unveiled plans to collaborate for the development of a broad portfolio of complex semiconductor intellectual property (IP) optimized for GLOBALFOUNDRIES’ leading-edge process technology.
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Imagination submits PowerVR Series6 cores for OpenGL ES 3.0 conformance (Monday Feb. 04, 2013)
Imagination Technologies announces that it is among the first to submit PowerVR Series6 ‘Rogue’ drivers for OpenGL ES 3.0 conformance with Khronos.
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Digital Core Design introduces Local Interconnect Network IP Core (Thursday Jan. 31, 2013)
Digital Core Design has presented a solution, which is fully compatible with the LIN 1.3, 2.1 and the newest version 2.2 Revision A, released by the LIN Consortium.
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Kilopass NVM IP Achieves JEDEC Qualification on High-Demand SMIC 65/55/40nm Processes (Wednesday Jan. 30, 2013)
Kilopass Secure NVM IP Qualified for 10-Year Life in Mobile Phone and Consumer Electronics SoCs on SMIC 65/55/40nm Low-Leakage CMOS Logic Processes
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Synopsys Announces Energy-Efficient 28-nm PCI Express 3.0 PHY with Support for 10GBASE-KR (Tuesday Jan. 29, 2013)
Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer (nm) Enterprise 10G PHY supports multiple interface standards, including PCI Express® (PCIe®) 3.0 and 10GBASE-KR, for a flexible interconnect solution.
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New 32-bit BA25 Application Processor Adds More Performance to Royalty-Free BA2x Family (Tuesday Jan. 29, 2013)
Beyond Semiconductor and CAST today unveiled a more powerful member of the BA2x Family of 32-bit processor IP cores. The new processor operates at high frequencies (more than 800 MHz and 1,360 DMIPS in 65 nm LP) yet maintains a smaller silicon footprint than most competing application processors.
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GUC Successfully Validates a 28nm GPU/CPU Platform (Tuesday Jan. 29, 2013)
GUC achieves test chip validation results for a complete 28nm System-on-chip that combines CPUs and GPUs on single technology platform.
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Posedge Launches 2x2 MIMO WLAN MAC and Baseband IP (Tuesday Jan. 29, 2013)
Posedge today announced the availability of MIMO WLAN, the best-in-class 2x2 Multi-Input, Multi-Output (MIMO) WLAN MAC and Baseband sub-system IP for next generation wireless LAN sub-system and system on a chip (SoC) designs.
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Rambus Introduces R+ Enhanced Standard Memory and Interface Solutions (Monday Jan. 28, 2013)
Rambus today introduced the Rambus R+™ family of enhanced standard solutions, specifically designed for the memory and interface market. The R+ family allows customers to differentiate their products in a cost-effective manner with improved time-to-market. Rambus solutions are also available with collaborative design and integration services to optimize design and development cycles.
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Rambus Introduces R+ LPDDR3 Memory Architecture Solution (Monday Jan. 28, 2013)
Rambus today announced its first LPDDR3 offering targeted at the mobile industry. In the Rambus R+ solution set, the R+ LPDDR3 memory architecture is fully compatible with industry standards while providing improved power and performance.
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Evatronix Adds the Scaling Capabilities to its PANTA DP20 Display Processor (Monday Jan. 28, 2013)
Utilizing latest ARM technology like TrustZone and AXI4 the PANTA DP20 is targeted specifically at high-end mobile/portable products, like smartphones and tablets, with ultra-low power consumption and impressive processing performance.
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intoPIX Launches new compact JPEG2000 Encoder and Decoder FPGA IP-cores at ISE 2013 (Friday Jan. 25, 2013)
intoPIX launches its customizable reference applications for JPEG 2000 targeting the smallest 28nm FPGA devices from Altera and Xilinx at ISE 2013.
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Updated IDE and Latest GCC Toolset Improve Application Development for BA2x Family Processors (Tuesday Jan. 22, 2013)
A new version of the BeyondStudio™ Integrated Development Environment (IDE) eases software development and upgrades compilation and debugging features. It works with the BA2x Family of 32-bit processor IP cores developed by Beyond Semiconductor and available from CAST, Inc.
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IP Cores, Inc. Announces Additional Shipments of the LZR3 Scalable Lossless Data Decompression IP Cores (Tuesday Jan. 22, 2013)
IP Cores, Inc. announces more shipments of the cores from its LZR3 high-speed lossless data decompression IP core family with very low decompression latency.
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eMemory's NeoEE SIP Qualified for 2.4GHz RF Product Application (Monday Jan. 21, 2013)
eMemory announced new breakthroughs in the applications of its Multiple Times Programmable (MTP) eNVM NeoEE® SIP. The 2.4GHz Radio Frequency Integrated Circuit (RFIC), which utilizes NeoEE® SIP, has recently been qualified in a number of foundries and will soon go into mass production.
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Arasan Chip Systems Announces the Most Complete ONFI 3.1 NAND Controller IP & PHY Solution (Thursday Jan. 17, 2013)
Arasan announced today the availability of the most complete solution of ONFI 3.1 NAND Controller IP & PHY, including ONFI 3.1 compatible NV-DDR2 I/O pads. Arasan has ported its ONFI 3.1 NV-DDR2 I/O pads in to advanced process running at 400 MT/s with 200 Mhz clock.
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Elliptic Technologies Introduces New Multi-Protocol Security Engine To Support Home/Office Networking and LTE Small Cell Applications (Thursday Jan. 17, 2013)
Elliptic Technologies today announced a new highly integrated IPsec/TLS Multi-Protocol Security Engine to address the security needs of residential gateways, VPN appliances and LTE small cells.
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Intilop delivers true Ultra-low latency 10G NIC with their 5th Gen 76 ns TCP & UDP Offload technology breaking yet another record in latency and bandwidth (Thursday Jan. 17, 2013)
Intilop today announced delivery of a true ultra-low latency NIC + System Platform powered by their new Ultra Low latency 5th Gen 10G Nano TOE/UOE, Ultra Low latency Media Access controller, Ultra-low latency PCIe/DMA and ultra-precise time-stamping capability.
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Archband achieves SMIC qualified 96dB Hi-Fi Audio CODEC IP in 65nmLL process (Thursday Jan. 10, 2013)
Archband today announced the immediate availability of its second generation silicon proven, low power and high performance stereo audio CODEC IP AR82S01 in SMIC 65nmLL logic process.
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Imagination pushes the boundary for existing PowerVR Series5XT (SGX) GPUs with new extended API features (Tuesday Jan. 08, 2013)
Imagination Technologies announces a set of advanced API extensions for its existing PowerVR Series5XT (SGX) GPUs, giving application processors using the technology, and mobile and embedded devices based on them, access to some of the features that would otherwise be only available on future APIs on next generation GPUs.
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Digital Blocks Extends its I2C Controller IP Core Family with Enhanced Capabilities & System-Level Features (Tuesday Jan. 08, 2013)
Digital Blocks today announces the extension of its DB-I2C-MS / DB-I2C-M / DB-I2C-S I2C Controller IP Core family.








