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IP / SOC Products News

• Xylon Announces logiSPI SPI to AXI4 Controller Bridge IP Core for Xilinx Zynq-7000 AP SoC and FPGAs (Monday Jan. 07, 2013)
  New logiSPI SPI to AXI4 Controller Bridge IP core from Xylon's logicBRICKS™ IP library enables easy inter-chip board-level interfacing between virtually any microcontroller (MCU) and Xilinx® Zynq™-7000 All Programmable SoC and FPGAs through the Serial Peripheral Interface (SPI) bus.
  
  
• Allegro DVT showcases the first HEVC video hardware decoder IP at CES 2013 (Thursday Jan. 03, 2013)
  Allegro DVT will present its HEVC Video Hardware Decoding IP, the world first HEVC hardware decoder IP targeting mobile phones, tablets, set-top boxes, digital TVs... This IP can be implemented both on FPGA and SoC, supports any resolution up to 4K, and is optimized in terms of silicon area, power consumption and memory bandwidth.
  
  
• Digital Core Design introduces DQSPI - quad performance SPI (Thursday Jan. 03, 2013)
  Serial Peripheral Interface – Master/Slave with not only single and dual but most of all quad SPI Bus support, is the newest IP Core introduced by Digital Core Design. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. IP Core supports all 8, 16, 32 bit processors and has been designed to offer the fastest available operations for any serial memory.
  
  
• Tensilica Introduces the Smallest, Lowest Power DSP IP Core For Always-Listening Voice Trigger and Voice Recognition (Thursday Jan. 03, 2013)
  Tensilica today introduced the HiFi Mini DSPcore, the smallest, lowest power DSP IP core supporting always listening voice trigger and speech command modes.
  
  
• ARM and Cadence Tape Out First 14nm FinFET Test Chip Targeting Samsung Process (Friday Dec. 21, 2012)
  ARM and Cadence today announced the tape-out of the first 14-nanometer test chip implementation of the high-performance ARM Cortex-A7 processor, the most energy-efficient applications processor from ARM.
  
  
• Vivante Shipping World's Smallest and Lowest Power OpenGL ES 3.0 IP Core (Wednesday Dec. 19, 2012)
  Vivante today announced another major milestone in its leading multi-core GPU IP family: The world’s tiniest GPU core designed* to support the Khronos™ Group’s OpenGL® ES 3.0 API based on the GC880 IPleveraging the same ScalarMorphic™ technology of Vivante's industry leading multi-core ultra-threaded GPU cores.
  
  
• HDL Design House MIPI M-PHY and D-PHY Solutions available in 40nm and 65nm (Tuesday Dec. 18, 2012)
  HDL Design House today announced availability of MIPI M-PHY and D-PHY solutions in advanced technology nodes. MIPI M-PHY and D-PHY solutions are fully compliant with the MIPI Alliance M-PHY and D-PHY specifications version 1.0, as the latest addition to HDL Design House FlexIP core library.
  
  
• CEVA and Orca Partner to Deliver Complete Bluetooth 4.0 Reference Design for Integration into Mobile Computing, Consumer Electronics Devices (Wednesday Dec. 12, 2012)
  CEVA today announced a collaboration with Orca Systems to offer a complete reference design platform for Bluetooth 4.0. The combined offering integrates Orca's Bluetooth Radio with CEVA's Bluetooth 4.0 baseband and software stack IP for a low cost, complete licensable solution.
  
  
• Reflex CES Introduces Industry's First Aurora-Like IP Core, Offers Freedom to Choose Best FPGA Technology by Enabling Interoperability between Leading FGPA Platforms (Wednesday Dec. 12, 2012)
  Reflex CES today announced the industry’s first release of the Reflex CES Aurora-like IP Core based on Altera FPGAs. The core enables interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs.
  
  
• Novocell Smartbit Antifuse OTP NVM Memory Validated at IBM Foundry at Processes from 350nm to 130nm (Wednesday Dec. 12, 2012)
  Novocell has announced the completion of multi-node intellectual property validation within IBM Foundry’s “Ready for IBM Technology” program.
  
  
• Xylon Showcases the World's Fastest 3D Graphics Engine for Xilinx Zynq-7000 All Programmable SoC (Tuesday Dec. 11, 2012)
  Xylon has ported company's 3D Graphics Processing Unit (GPU) to the Xilinx® Zynq™-7000 All Programmable SoC ZC706 Evaluation Kit. The Xilinx ZC706 evaluation board features the XC7Z045 FFG900-2 SoC with the Xilinx 7 Series Kintex™-7 FPGA equivalent programmable logic.
  
  
• Arasan Chip Systems further expands its Ethernet portfolio by adding AVB (Audio Video Bridging) (Monday Dec. 10, 2012)
  Arasan announced today that they have added AVB (Audio Video Bridging) to their Gigabit Ethernet MAC product family. The new Gigabit Ethernet MAC with AVB enables the transmission of audio and video streams synchronized within a microsecond of each other, with low delay, and with minimal lost data due to network congestion.
  
  
• Creonic Announces MMSE MIMO Detector IP Core (Monday Dec. 10, 2012)
  Creonic today announced the availability of a high-efficiency MMSE MIMO detector IP core for February 2013. The Creonic MMSE MIMO detector IP core offers high throughputs even on low-cost FPGAs and is convincing with its low implementation complexity at the same time.
  
  
• GUC Monthly Sales Report - November 2012 (Monday Dec. 10, 2012)
  GUC today announced its net sales for November 2012 were NT$815 million, up 3.3% month-overmonth and up 6.4% year-over-year.
  
  
• HDL Design House Introduces MIPI CSI-2 Transmitter IP core (Friday Dec. 07, 2012)
  HDL Design House today announced availability of MIPI CSI-2 Transmitter (HIP 3900), digital core that is compliant with the MIPI Alliance CSI-2 Specification, as part of HDL Design House FlexIP core library.
  
  
• Dolphin Integration first to achieve 0.84 pA per bit in SpRAM at the 90 nm uLL embedded flash process (Friday Dec. 07, 2012)
  Dolphin Integration announces that the memory architecture RHEA, achieving leakage as low as 0.84 pA/bit at 90 nm uLL embedded flash process has now passed the pre-silicon assessment criteria (Level 1) of TSMC’s stringent IP9000 qualification program.
  
  
• Latest Release of MIPS Architecture Includes Virtualization and SIMD (Thursday Dec. 06, 2012)
  MIPS Technologies today publicly announced a major release of the MIPS® architecture, encompassing the MIPS32®, MIPS64® and microMIPS™ instruction set architectures.
  
  
• Elliptic Offers Highest Protection for Premium Content with HDCP 2.2 Compliant Solutions (Wednesday Dec. 05, 2012)
  Elliptic Technologies today announced support for the recently released High-bandwidth Digital Content Protection 2.2 (HDCP 2.2) specification for premium content delivery and distribution.
  
  
• Kilopass First to Demonstrate Antifuse Non-Volatile Memory IP With Successful Test Chips on TSMC 20nm Process (Tuesday Dec. 04, 2012)
  Kilopass today announced that its NVM IP is the first antifuse technology to achieve successful test chips on TSMC’s 20nm process. Analysis of the test chips containing Kilopass NVM IP memory modules validated manufacturability, process control tolerance and cell programming characteristics.
  
  
• Arasan Chip Systems Announces MIPI conformant Camera Serial Interface (CSI-3) Receiver IP Core (Monday Dec. 03, 2012)
  Arasan announced today the addition of MIPI Alliance CSI-3 Receiver IP along with a matching Type 1 M-PHY to the company’s expansive MIPI portfolio. The CSI-3 Receiver and M-PHY’s can be delivered to customers in configurations of 1 to 4 receive lanes.
  
  
• PLDA and GUC Announce Industry's First Successful PCIe Gen 3 Controller and PHY Combination on TSMC's 28nm HPM Process Technology (Monday Dec. 03, 2012)
  PLDA today announced successful test chips for the industry’s first combined PCIe Gen 3 Controller IP and PHY IP solution on TSMC 28nm HPM (High Performance Mobile) process. The combined PCIe 3.0 Controller/PHY solution is in initial production and has been incorporated into demo boards.
  
  
• RivieraWaves Achieves 802.11n Certification; Announces Wi-Fi 802.11ac Silicon IP (Monday Dec. 03, 2012)
  RivieraWaves announced IEEE Wi-Fi 11n certification of its new scalable Wi-Fi 802.11ac silicon IP. The IP is available in a broad range of configurations, supports 802.11n and 802.11ac specifications, single or multiple MIMO (Multiple-Input and Multiple-Output) streams, and up to four transmit and receive antennas.
  
  
• GUC Delivers 28nm DDR3-2133/LPDDR2 Combo IP (Monday Dec. 03, 2012)
  Global Unichip Corp. (GUC) today announced that it has added a DDR3-2133/LPDDR2 combination PHY and Controller IP to its extensive portfolio of 28nm silicon-proven IP portfolio.
  
  
• DRPIC166X MCU, low-cost mixed with high performance (Friday Nov. 30, 2012)
  The good old fashioned PIC microcontrollers are finding their way into new applications like smartphones, gaming peripherals, audio devices and embedded solutions for eg innovative medical devices. Moreover, because the DRPIC166X has upward compatible architecture, it preserves investment in code development. And if it’s not enough, let’s just mention that DCD’s IP Core offers 1.3GHz virtual clock frequency and consumes just 37uW/MHz.
  
  
• World's first ITU-T G.729A compliant Voice Codec Hardware Accelerator by Noesis Technologies (Tuesday Nov. 27, 2012)
  Noesis Technologies announced today the immediate availability of its ITU-T G729A compliant voice codec IP Core. The ITU-T G.729A CS-ACELP is a high speech quality, low-bit rate (8kbps) codec that has been proposed to meet the voice compression requirements of a modern communication system.
  
  
• CAST Offers H.264 High-Profile Encoder IP Core for FPGAs and ASICs (Tuesday Nov. 27, 2012)
  An H.264 High Profile video encoder IP core is now available from semiconductor intellectual property provider CAST, Inc. Intended for demanding high-definition applications like HD broadcast, professional video cameras, and video storage, the new High Profile H.264/AVC Video Encoder Core offers exceptional video quality, competitive performance, and easy system integration.
  
  
• Tensilica and mimoOn Partner to Provide the Only Comprehensive LTE and LTE-Advanced Hardware-Software PHY IP Solution (Tuesday Nov. 27, 2012)
  Tensilica and mimoOn today announced a tight partnership to provide designers with the only comprehensive hardware/software licensable IP solution for LTE (Long-term evolution) and LTE-Advanced chip designs. Through an agreement between mimoOn and Tensilica, Tensilica is now the exclusive DSP IP vendor for mimoOn’s LTE UE (user equipment) and eNodeB (base station) physical layer (PHY) software products.
  
  
• HDL Design House Announces MIPI DSI (Controller + D-PHY) IP Solutions (Monday Nov. 26, 2012)
  HDL Design House has announced availability of MIPI DSI Host (HIP 3500) and Peripheral (HIP 3510) IP cores, fully compliant with the MIPI Alliance DSI specification, as part of HDL Design House FlexIP core library.
  
  
• Dolphin Integration introduces a new generation of SpRAM at 55 nm (Monday Nov. 26, 2012)
  Dolphin Integration is releasing RHEA, the latest memory architecture of its SpRAM family, for power and cost sensitive SoCs at 55 nm TSMC technological processes.
  
  
• Cosmic Circuits' announces silicon proven MIPI M-PHY in multiple 28nm flavors, provides complete offering for a mobile platform (Friday Nov. 23, 2012)
  Cosmic Circuits M-PHY solution supports both the HS-G1 (1.5Gbps) and HS-G2 (3Gbps) modes and is available in multiple process technologies ranging from 85nm to 28nm. Cosmic Circuits M-PHY offering in 28nm now includes solutions for integration in baseband modems that typically targets a low-leakage process and application processors that target the high-performance process.