D&R Headline News | Most Popular | SoC News Alerts | |

IP / SOC Products News

• V Semi Announces Availability of New IP (Friday May. 11, 2012)
  V Semiconductor Inc. (V Semi) has announced today the availability of its State-of-the-Art Digital PLL IP cores in several new technology nodes and foundries. The foundries include TSMC, UMC and the Common Platform Alliance. The IP cores have been Silicon proven and successfully characterized. Full characterization reports are now available.
  
  
• MIPS Technologies Introduces New Aptiv Generation of Microprocessor Cores (Thursday May. 10, 2012)
  MIPS Technologies today introduced a new generation of microprocessor cores. The Aptiv Generation cores, including the proAptiv, interAptiv and microAptiv families, offer three distinct performance levels for applications across MIPS' target segments.
  
  
• Evatronix Launches Display Processor based on Latest ARM Security Technology (Monday May. 07, 2012)
  Evatronix SA has announced the release of the first member of its PANTA high performance display controller core family. Developed using ARM technology the PANTA DP20 is targeted specifically at high-end mobile/portable products, like smartphones and tablet PCs, with ultra-low power consumption that does not sacrifice processing performance.
  
  
• DMP Introduces High-End OpenGL ES 2.0 IP Cores and Multi-Core Configurations to Its SMAPH-S Product Family (Monday May. 07, 2012)
  DMP today ann1ounced significant product expansion to its scalable SMAPH-S shader based Graphics IP Core product family including new high-end and OpenGL ES 2.0 compliant IP cores with multi core deployment (MP) support that offers the industry leading graphics rendering and computing performance.
  
  
• PLDA Introduces QuickTCP - Full Hardware 10G TCP/IP Stack IP core for FPGA (Thursday May. 03, 2012)
  PLDA today unveiled its 10Gb TCP/IP Hardware stack IP core. PLDA’s QuickTCP IP solution is a 100% RTL designed IP, compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and TCP protocols. QuickTCP features an industry-standard AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs.
  
  
• Cosmic Circuits announces silicon-proven PLLs in multiple process nodes (Wednesday May. 02, 2012)
  The system-clocking PLLs are implemented in 110nm and 28nm process technology, and will offer SoC designers a wide range of analog and digital PLLs to choose from – these include PLLs that support input frequencies ranging from 32 kHz- 2000 MHz without requiring any external components, PLLs that occupies extremely low core area, and spread-spectrum PLLs for EMI suppression.
  
  
• Arasan Chip Systems Announces MIPI compliant Low Latency Interface (LLI) IP solution (Wednesday May. 02, 2012)
  Arasan announced today the availability of their MIPI LLI controller IP along with a matching Type 1 M-PHY, the latest additions to its prominent MIPI portfolio.
  
  
• Imec demonstrates a low-power 7Gbps 60GHz transceiver for the wireless consumer market (Wednesday May. 02, 2012)
  Imec, in collaboration with Panasonic, has developed a prototype of a 60GHz radio transceiver allowing to reach data rates of 7Gbps over short distances at very low power consumption. The chip achieves this performance over the 4 channels specified by the IEEE802.11ad standard.
  
  
• Elecard announces UpScaler IP Core for design and development of video-output devices (Thursday Apr. 26, 2012)
  Today, Elecard Devices CJSC announced release of Elecard UpScaler IP Core, a functional unit which is designed for image resolution upscaling (zooming) in the process of image output at the display device. Scaling coefficient can be set to any value.
  
  
• D16950 UART - All in One with IRDA onboard (Tuesday Apr. 24, 2012)
  Digital Core Design introduced its latest UART core. It offers full compatibility with the most popular industry standards: 450, 550, 650, 750 and of course 950. Moreover, DCD’s IP supports IRDA data format mode, which combined with unique multitasking makes this IP Core one of the most advanced and flexible UART core.
  
  
• Dolphin Integration highlights an innovative solution to improve drastically the performance of Embedded Flash memories (Friday Apr. 20, 2012)
  Dolphin Integration reveals its latest innovations. The leading product of the new offering enables the “Apparent NVM Memory”, namely the Stratus cache controller, as it reverses the traditional looks: it is not tied to a single processor for mere speed, nor limited to specific access statistics.
  
  
• ARM Announces Cortex-A15 Quad-Core Hard Macro (Tuesday Apr. 17, 2012)
  ARM today announced the availability of a high performance, power-optimized quad-core hard macro implementation of its flagship Cortex(TM)-A15 MPCore(TM) processor.
  
  
• Barco Silex delivers its JPEG 2000 IP cores on all 28nm FPGA platforms (Monday Apr. 16, 2012)
  Barco Silex announces the support of its JPEG 2000 IP cores on all families of 28nm FPGA devices
  
  
• CEVA Introduces CEVA-TeakLite-4 -- The Most Powerful, Low Power 32-bit DSP Architecture Framework for Advanced Audio and Voice Applications (Monday Apr. 16, 2012)
  Built on the proven foundation of the widely-used CEVA-TeakLite family, the CEVA-TeakLite-4 introduces innovative smart power management technology and supports customer-owned extensions, making it a highly flexible architecture and ideal for even the most area and power sensitive designs.
  
  
• ARM Expands Processor Optimization Pack Solutions for TSMC 40nm and 28nm Process Variants (Monday Apr. 16, 2012)
  ARM today announced the availability of a significantly expanded lineup of ARM(R) Processor Optimization Pack(TM) (POP) solutions for TSMC 40nm and 28nm process technologies targeting a range of ARM Cortex(TM) processors. At least nine new POP configurations targeting Cortex-A5, Cortex-A7, Cortex-A9 and Cortex-A15 processor cores will be released.
  
  
• intoPIX announces new JPEG 2000 & security IP-cores optimized for the 28nm FPGAs (Wednesday Apr. 11, 2012)
  intoPIX announced today that the first JPEG 2000 encoder and decoder IP-cores optimized for the new 28nm FPGAs will be released by the end of Q2 2012.
  
  
• intoPIX enhances its JPEG 2000 IP-cores with the support of the new Broadcast profile (Friday Apr. 06, 2012)
  intoPIX announced today the release of its new generation of JPEG 2000 FGPA IP-cores supporting the Broadcast profile (JPEG 2000 Part 1 Amd 3 – Profiles for Broadcast Application - ISO/IEC 15444-1:2004/Amd3). The new intoPIX JPEG 2000 IP cores implementation enable the Broadcast industry to focus on increased interoperability for broadcast contribution and for mezzanine applications.
  
  
• Sital's EBR-1553 IP Core is Now Available (Thursday Apr. 05, 2012)
  Sital Technology's Enhanced Bit Rate (EBR) 1553 Intellectual Property core for FPGA is now available. EBR-1553 is a 10Mbps bit rate protocol which utilized the robust Mil-Std-1553 protocol over RS-485 transceivers in a hub-based point-to-point connection. Using network topology of a star between BC and Remote Terminals enables high-speed and robust data transfer.
  
  
• Intilop Corporation announces the release and delivery of their highly customizable 3rd generation 10G Ultra-Low Latency and High Performance Ethernet MAC (Thursday Apr. 05, 2012)
  Intilop today announced their new 3rd Gen 10G Ultra-Low-Latency Ethernet Media Access controller (EMAC) IP cores based around enhanced Architecture. These Industry leading Ultra-Low latency 10G EMAC IP products have fully integrated scalable BRAMs and optional PCIe/DMA Engines.
  
  
• Novocell Semiconductor Announces NVM IP Tape Out at IBM 45nm – Brings 100 Percent Reliable Anti-Fuse One-Time Programmable Non-Volatile Memory to Advanced Node (Thursday Apr. 05, 2012)
  Novocell Semiconductor has announced that their industry leading OTP NVM IP has been taped out for a customer at the advanced 45nm node.
  
  
• Aliathon announces 100G Transponder & Muxponder Demo Design (Thursday Apr. 05, 2012)
  Aliathon announces the immediate availability of our 100G OTN dual Transponder / Muxponder demo design recently demonstrated to customers at OFC 2012.
  
  
• HDL Design House announces new TX and RX controller cores for the HDMI and DisplayPort standards (Wednesday Apr. 04, 2012)
  HDL Design House, a company that offers design and verification services as well as soft and hard IP cores (digital and analog), today announced the availability of soft IP TX and RX controller cores for the HDMI and DisplayPort standards.
  
  
• CEVA-TeakLite-III Becomes Industry's First DSP Core to Offer Optimized Skype SILK Super Wideband Speech Codec (Tuesday Apr. 03, 2012)
  Optimized for the 32-bit CEVA-TeakLite-III family of audio DSPs and forward compatible with future versions of the widely-used CEVA-TeakLite DSP architecture, CEVA's implementation of the SILK codec delivers a high quality, cost-efficient voice communications solution for both mobile and digital home applications, with significant power savings compared to alternative solutions.
  
  
• Memoir Systems Unveils First Commercial Product--Renaissance 2X Embedded Memory IP (Monday Apr. 02, 2012)
  Based upon the company’s award-winning Algorithmic Memory® technology which creates new multiport embedded memories by combining algorithms with standard 1-port SRAM, Renaissance 2X brings a revolutionary approach to embedded memory development across the semiconductor industry. Renaissance 2X offers four separate memory generators: a 2 port (1R1W), a dual port (2RW), and specialty memories for 2Ror1W and 1RW1W.
  
  
• Open-Silicon Unveils Interlaken IP Core with 600 Gbps Chip-to-Chip Interface Support for Networking, Storage and High-Performance Computing Products (Monday Apr. 02, 2012)
  Open-Silicon announced today version six of the company’s Interlaken IP core. This release offers tremendous implementation flexibility to customers by supporting SerDes data rates up to 28Gbps and multiple data width options. The IP core also conforms to the recently released “Interlaken Retransmit Extension” protocol definition from the Interlaken Alliance.
  
  
• Cosmic Circuits aims to be major player in Semiconductor IP, announces roadmap for PCI Express, USB3.0, USB2.0, HDMI & MIPI in 28nm and 20nm (Tuesday Mar. 27, 2012)
  Cosmic Circuits today announced the development of MIPI D-PHY, MIPI M-PHY, USB2.0, USB3.0, PCI Express and HDMI IPs in 28 and 20nm. Cosmic Circuits is also developing the controller solutions for these standards in order to provide customers with a complete solution.
  
  
• Analog Bits SERDES Achieves 10Gbps on Consumer Electronic Cables (Tuesday Mar. 27, 2012)
  Analog Bits unveiled a new cable-specific SERDES IP specifically targeting the cost-sensitive, yet performance demanding consumer cable market. The latest addition to the Analog Bits SERDES IP product line allows customers to use low cost cables with SERDES at either end to recover and retime the signal and has been demonstrated with multiple cables including FFC ribbon, Micro-Coax and Dual-Coax.
  
  
• Imagination announces highest performance 4K capable multicore video decoder (Tuesday Mar. 27, 2012)
  Imagination Technologies has announced the PowerVR VXD395MP video decoder with support for resolutions up to 4Kx2K thanks to a unique multicore architecture.
  
  
• Synopsys Unveils Industry's First Complete Audio IP Subsystem (Monday Mar. 26, 2012)
  Synopsys today announced the availability of the DesignWare® SoundWave Audio Subsystem, a complete, integrated hardware and software audio IP subsystem for system-on-chip (SoC) designs. Synopsys' SoundWave Audio Subsystem is fully configurable and supports 2.0 to 7.1 audio streams with 24-bit precision to meet the requirements of a broad range of audio applications such as digital TVs, set-top boxes, Blu-ray Discs, portable audio devices and tablets.
  
  
• Cadence Delivers High-Performance, Low-Power Design IP Supporting LPDDR3 Memory Standard (Wednesday Mar. 21, 2012)
  Designed to provide the high bandwidth and low power consumption required by smartphones and tablets, the Cadence LPDDR3 memory IP solution includes integrated controller and PHY support, virtual prototyping, verification IP and Allegro(R) design-in kits to accelerate implementation and reduce design risk.