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IP / SOC Products News

• Movea Launches Industry's First Motion Processing IP Cores designed for mobile devices (Thursday Feb. 23, 2012)
  Movea announced today its new MotionCore product line: a family of motion processing IP Cores designed for mobile devices. MotionCore architectures are optimized for motion sensing and data fusion applications and run implementations of Movea's proprietary SmartMotion® algorithms.
  
  
• Imec and Renesas Electronics report record ADC for next-generation high-bandwidth wireless receivers (Thursday Feb. 23, 2012)
  imec and Renesas report an innovative SAR (successive-approximation register) ADC (analog to digital converter) with a spectacular improvement in power efficiency and speed, targeting wireless receivers for next-generation high-bandwidth standards such as LTE-advanced and the emerging generation of Wi-Fi (IEEE802.11ac).
  
  
• VeriSilicon Releases New Generation of Hantro Video IP Products to Promote WebM and WebRTC (Thursday Feb. 23, 2012)
  VeriSilicon announces immediate availability of Hantro G1v5 Multi-format Decoder and Hantro H1v5 Multi-format Encoder semiconductor IPs which support 4K x 4K video, achieved through core enhancements and improved memory latency resiliency up to 600 cycles.
  
  
• Digital Core Design: World's fastest 80C51 CPU @ CeBIT (Thursday Feb. 23, 2012)
  Digital Core Design has introduced the world’s most advanced 80C51 architecture. DCD has achieved results which are more than 56 times better than standard 8051 and more than 70% more efficient, than the nearest competition.
  
  
• TES announces the availability of the D/AVE HD Graphics Processor for Embedded Systems (Wednesday Feb. 22, 2012)
  TES Electronic Solutions (“TES“) announces the availability of its new graphics processor, D/AVE HD. This processor is the third generation of rendering hardware IP-cores for embedded systems from TES.
  
  
• Cadence Expands Proven Ethernet IP Offering With 40/100 Gigabit Ethernet Solution (Tuesday Feb. 21, 2012)
  Cadence today announced 40/100 Gigabit Ethernet (GbE) media access controller (MAC) and physical coding sub-layer (PCS) IP cores that enable the rapid deployment of SoCs for networking and high-performance computing.
  
  
• CEVA Unveils the CEVA-XC4000 - A Low-Power DSP Architecture Framework for the Widest Array of Advanced Wireless Standards (Tuesday Feb. 21, 2012)
  CEVA-XC4000 offers unparalleled, scalable performance capabilities and innovative power management to address the most demanding communication standards, including LTE-Advanced, 802.11ac and DVB-T2, on a single architecture
  
  
• Tensilica Lays the Foundation for Software Programmable LTE-Advanced User Equipment PHY (Layer 1) in Less than 200mW (Tuesday Feb. 21, 2012)
  New ConnX BBE32UE Optimized DSP Core Coupled with Tensilica Dataplane Processors (DPUs) Enable Ultra-Low Power LTE-Advanced PHY
  
  
• Cortus announces Processor IP Roadmap for Embedded System on Chip (SoC) Applications (Tuesday Feb. 21, 2012)
  Cortus announces the expansion of its product range to include a total of four 32-bit embedded microcontroller cores addressing a wider market. The processor family builds on its production proven technology first released with the APS3 ultra low power core.
  
  
• Intilop TCP Offload Engine Delivers Full TCP Offload in Less than 100 nanoseconds Using Altera's Stratix IV FPGA (Monday Feb. 20, 2012)
  Intilop, Inc. a pioneer and a recognized leader in providing highly complex Ultra-Low latency networking Mega IP building blocks, systems and solutions, announced they will showcase their 4th Gen. SX-Series 10G Ultra-Low latency TOE + EMAC + Altera_PHY Mega IP cores running on Stratix® IV FPGA.
  
  
• PLDA Introduces QuickPCIe - PCI Express Interface IP With Enhanced DMA (Friday Feb. 17, 2012)
  PLDA today announced QuickPCIe - the industry's most advanced PCI Express interface IP solution featuring a high performance configurable DMA. QuickPCIe is a revolutionary breakthrough in IP integration, standardizing on the AMBA(R) AXI open interconnect protocol to provide a unified and scalable interface to user logic.
  
  
• Elliptic Extends Leadership In Security IP With DVB CSA3 Descrambler For Digital TV Broadcasting (Thursday Feb. 16, 2012)
  Elliptic Technologies announced that it has released the DVB CSA3 Descrambler, a security core that supports the latest generation of conditional access specifications licensed by the European Telecommunications Standards Institute (ETSI) and adopted by the Digital Video Broadcasting (DVB) consortium .
  
  
• MoSys Demonstrates Bandwidth Engine IC Interoperability with LSI SerDes (Wednesday Feb. 15, 2012)
  MoSys has successfully demonstrated interoperability of its Bandwidth Engine® IC with the SerDes characterization and evaluation board from LSI Corporation.
  
  
• Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nanometer Processes (Tuesday Feb. 14, 2012)
  Synopsys today announced immediate availability of DesignWare® Embedded Memory and Logic Library IP for TSMC's 28-nm high-performance (HP) and high-performance for mobile (HPM) process technologies.
  
  
• Synopsys Announces Industry's First HDMI 1.4 PHY IP in 28-nanometer Processes for Multiple Foundries (Tuesday Feb. 14, 2012)
  Synopsys today announced the immediate availability of DesignWare® HDMI (High-Definition Multimedia Interface) 1.4 PHY IP in advanced 28-nanometer (nm) processes for multiple leading foundries.
  
  
• Aliathon Ltd. Announces the immediate availability of their 100G OTN Transponder Reference Design For XILINX FPGAs. (Thursday Feb. 09, 2012)
  Aliathon Ltd. today announces the immediate availability of their 100G Transponder FPGA reference design, available for evaluation on the Xilinx Virtex-6 HXT FPGA ML630 Evaluation Kit.
  
  
• Evatronix Strengthens its Multimedia IP Portfolio with a Complete Series of MIPI SLIMbus Products (Thursday Feb. 09, 2012)
  Evatronix SA introduced today the complete series of Mobile Industry Processor Interface (MIPI) Alliance SLIMbus IP cores that implement next-gen serial interface for low power multimedia applications, especially mobile. The design is already proven to seamlessly operate as a key component within the SLIMbus to I2S bridge from LnK.
  
  
• Kilopass XPM Non Volatile Memory IP Qualified on TowerJazz 130nm CMOS (Tuesday Feb. 07, 2012)
  Kilopass Technology today announced that its XPM embedded OTP anti-fuse NVM IP has successfully completed 1000 hours of JEDEC 47 standard qualification for the 130nm G CMOS process at TowerJazz
  
  
• Sonics and Tensilica Team to Increase IP Integration, SoC Efficiencies (Thursday Feb. 02, 2012)
  Sonics today announced that its advanced on-chip networks will support Tensilica’s processor interface (PIF) to maximize customers’ IP integration and SoC efficiencies.
  
  
• Think Silicon GPUs get JPEG decoding from Alma Technologies (Thursday Feb. 02, 2012)
  Think Silicon Ltd and Alma Technologies announced today the immediate availability of Graphics Accelerator IP Cores preintegrated and verified with the silicon-proven JPEG cores of Alma Technologies.
  
  
• CEVA Announces Availability of Silicon-Based CEVA-XC Software Development Kit for the Rapid Design of Multi-Mode, Software-Defined Modems (Wednesday Feb. 01, 2012)
  CEVA today announced the availability of a new silicon-based, software development kit (SDK) for runtime software development based on the CEVA-XC323 DSP architecture. The CEVA-XC323 silicon embedded in the SDK was designed by CEVA and manufactured on a 65nm process, delivering up to 800MHz performance.
  
  
• Digital Blocks Expands Video Signal & Image Processing IP Core Family (Tuesday Jan. 31, 2012)
  The Digital Blocks new Video Signal & Image Processing IP Cores include a Color Space Converter, Chroma Resampler, CCIR BT.656 Encoder & Decoder, and system-level IP for RGB-to-CCIR 601/656 conversion.
  
  
• Evatronix Announces the USB 3.0 Compatible High Speed Hub IP Core with Analog and Digital PHY Options (Monday Jan. 30, 2012)
  Evatronix SA have announced a synthesizable USB High Speed Hub that supports High Speed mode requirements of the USB 3.0 Hub specification, and features an aggressive power management function provided by Link Power Management (LPM) mode for all supported speed rates.
  
  
• Systemcom Ltd announces silicon validated Current-Input Analogue Front End IP module (Friday Jan. 27, 2012)
  Systemcom Ltd announces silicon validated Current-Input Analogue Front End IP module, designed like sensor signal interface, primarily intended for processing current given by the sensor at the input of electronic system.
  
  
• Elliptic Technologies Debuts Security Engine For 4G LTE Mobile Backhaul Applications (Wednesday Jan. 25, 2012)
  Elliptic Technologies has announced the release of its IPsec Security Protocol Processor, SPP-230, to address the security needs of the 4G LTE mobile backhaul networks. This unique security engine accelerates IPsec packet processing to allow for multi Gbps performance by providing complete IPv6 ESP and AH packet transforms support.
  
  
• Open-Silicon's Configurable Interlaken IP Core Delivers High-Performance Chip to Chip Interface for Networking Products at 28nm Process Node (Monday Jan. 23, 2012)
  Open-Silicon announced today that the company’s Interlaken IP core has been used in over thirty implementations, and now includes silicon success in 28nm.
  
  
• Moortec Semiconductor Demonstrates Temperature Sensor IP on Low-Geometry Technologies (Monday Jan. 16, 2012)
  Moortec Semiconductor has demonstrated its high-performance analog IP on TSMC's 40LP and 28HP processes. The temperature sensor has been designed using standard CMOS logic processes for 40-nanometer (nm) and 28-nm geometries and can be easily instantiated multiple times across a System-on-Chip (SoC) for die temperature profiling.
  
  
• CAST Shipping New CAN Bus Controller IP Core (Monday Jan. 16, 2012)
  A new core from semiconductor intellectual property (IP) provider CAST, Inc. adds new capabilities to the company’s long-time support for the Controller Area Network (CAN) Bus Protocol. Sourced from partner Fraunhofer IPMS and available now, the CAN-CTRL CAN Bus Controller IP Core conforms to the latest, 2.0B CAN Bus Protocol and ISO ISO 11898-1 Data Link Layer specifications.
  
  
• Posedge Inc. Unveils "Multifunction Non-Volatile Memory Controller IP Platform" for SOC designers (Monday Jan. 16, 2012)
  The bundled IP Platform’s Development board has the ability to choose any memory solution like Serial Flash, NAND Flash, NOR Flash, SRAM or SD/eMMC memory. It has all the required connectors for SD/MMC devices and plug-in sockets for NAND/NOR/Serial Flash/SRAM ICs.
  
  
• Intilop Corporation announces release of a whole new series of 4th Gen Ultra-Low latency; sub 100 ns, Full TCP Offload and UDP Offload Engines and System solutions for the entire Network Communication sector (Wednesday Jan. 11, 2012)
  Intilop today announced new 4th Gen SX-Series TCP Offload and UDP Offload IPs based around enhanced TOE Architecture, these Industry leading Ultra-Low latency 10G TOE and UOE IP products have fully integrated EMAC and optional PCIe/DMA, as a system, is geared to provide Ultra-High performance NIC functionality also.