D&R Industry Articles | Most Popular | SoC News Alerts |

IP / SOC Products Articles

• SoCs challenge production test methods (Oct. 24, 2003)
  SoCs challenge production test methods
  
  
• Serial storage SoCs demanding to test (Oct. 24, 2003)
  Serial storage SoCs demanding to test
  
  
• Scan-based transition-fault test can do job (Oct. 24, 2003)
  Scan-based transition-fault test can do job
  
  
• Open architecture ATE tackles test woes (Oct. 24, 2003)
  Open architecture ATE tackles test woes
  
  
• Vectorless test: best bet for high-speed I/O (Oct. 24, 2003)
  Vectorless test: best bet for high-speed I/O
  
  
• Traveling at the speed of memory (Oct. 24, 2003)
  Traveling at the speed of memory
  
  
• Source-synchronous clocks pose challenges (Oct. 24, 2003)
  Source-synchronous clocks pose challenges
  
  
• Architecture-based vs. flow-based approach to DFT (Oct. 24, 2003)
  Architecture-based vs. flow-based approach to DFT
  
  
• ASICs demand test perspective (Oct. 20, 2003)
  ASICs demand test perspective
  
  
• Why platform-based design works better than a discrete IP approach (by David Fritz, ARC International) (Oct. 17, 2003)
  Why platform-based design works better than a discrete IP approach (by David Fritz, ARC International)
  
  
• Network DRAMs Shine in Datapath Designs (Oct. 16, 2003)
  Network DRAMs Shine in Datapath Designs
  
  
• Design of Base I/O Libraries (by Ron Nikel, Co-Founder and CTO of TriCN) (Oct. 14, 2003)
  Design of Base I/O Libraries (by Ron Nikel, Co-Founder and CTO of TriCN)
  
  
• Rapidly Implementing Synthesizable ARM IP (By Alan Gibbons, Synopsys and John Biggs, ARM) (Oct. 13, 2003)
  Rapidly Implementing Synthesizable ARM IP (By Alan Gibbons, Synopsys and John Biggs, ARM)
  
  
• Under the Hood of Library IP (by Brani Buric and Mike Colwell, Virage Logic) (Oct. 10, 2003)
  Under the Hood of Library IP (by Brani Buric and Mike Colwell, Virage Logic)
  
  
• Lifelong testing prescribed for complex chips (Oct. 06, 2003)
  Lifelong testing prescribed for complex chips
  
  
• Commentary: Synopsys memory IP users seek RTL source code (Oct. 03, 2003)
  Commentary: Synopsys memory IP users seek RTL source code
  
  
• Selecting PLLs for ASIC Applications requires tradeoffs (Sep. 26, 2003)
  Selecting PLLs for ASIC Applications requires tradeoffs
  
  
• SoC: Stuck in the mud or Charging ahead? (Sep. 23, 2003)
  SoC: Stuck in the mud or Charging ahead?
  
  
• Computing dons new suits as required (Sep. 23, 2003)
  Computing dons new suits as required
  
  
• Transceiver design is fully integrated (Sep. 22, 2003)
  Transceiver design is fully integrated
  
  
• System-In-Package or System-On-Chip? (Sep. 19, 2003)
  System-In-Package or System-On-Chip?
  
  
• Silicon segmentation (Sep. 18, 2003)
  Silicon segmentation
  
  
• Decoupling Echo Cancellation from DSPs in VoP Gateways (Sep. 18, 2003)
  Decoupling Echo Cancellation from DSPs in VoP Gateways
  
  
• PLLs Plot An Adjustable Course (Sep. 12, 2003)
  PLLs Plot An Adjustable Course
  
  
• Making Interconnects More Flexible (Sep. 10, 2003)
  Making Interconnects More Flexible
  
  
• Analogue synthesis for SoC (Sep. 05, 2003)
  Analogue synthesis for SoC
  
  
• Software-Rich Chips (Aug. 29, 2003)
  Software-Rich Chips
  
  
• Pressure is on Third-Party Memory IP (Aug. 28, 2003)
  Pressure is on Third-Party Memory IP
  
  
• Configurable processors or RTL -- evaluating the tradeoffs (Aug. 27, 2003)
  Configurable processors or RTL -- evaluating the tradeoffs
  
  
• Multi-core multi-threaded SoCs pose debugging hurdles (Aug. 19, 2003)
  Multi-core multi-threaded SoCs pose debugging hurdles