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IP / SOC Products News

• Dolphin Integration announces breaking density records with the AURA Single Port memory registers (1PRFile) at 65 nm LP (Monday Jun. 20, 2011)
  Using the 1PRFile AURA generator leads to die cost decreased as much as 50% and to power consumption halved in comparison with alternative solutions.
  
  
• Arasan Chip Systems Introduces MMC/e.MMC 4.5 Host Controller IP (Friday Jun. 17, 2011)
  Arasan announced today the introduction of its MMC/eMMC 4.5 Host Controller IP product. Arasan’s MMC/eMMC 4.5 Host Controller is the first to support the new specification, released by JEDEC, that is designed to meet requirements for secure yet flexible program code and data storage for consumer electronic products.
  
  
• Rambus Develops Breakthrough Clocking Technology for Power Reduction in High-Speed Interfaces (Wednesday Jun. 15, 2011)
  Rambus today announced the development of a fast power-on, low-power clocking technology that can enable a whole new class of memory devices. Implemented in a 40nm low-power CMOS process, this technology is capable of transitioning from a zero-power idle state to a 5+ Gb/s data transfer rate in 5 nanoseconds (ns) while achieving active power of only 2.4mW/Gb/s.
  
  
• AES performance and flexibility boosted by Barco Silex with its innovative BA411E crypto engine (Wednesday Jun. 15, 2011)
  Barco Silex has announced the enhanced version of its multi-purpose AES crypto engine. Just like its predecessor, the BA411E supports a wide range of ciphering modes and offers an outstanding ratio performances/resources for ASIC and FPGA.
  
  
• Imagination launches POWERVR FRC271 Frame Rate Conversion IP Core (Tuesday Jun. 14, 2011)
  Imagination Technologies announces its latest frame rate conversion (FRC) IP core POWERVR FRC271, delivering full motion estimation motion compensation (MEMC) frame rate conversion to 1080P240 in a silicon area from under 1.5 mm2 in 40LP.
  
  
• RF Engines Releases ChannelCore Flex - the World's Most Flexible Ultra-Wideband Channelizer Solution (Tuesday Jun. 14, 2011)
  RF Engines Limited (RFEL) has taken a large step towards this goal with the introduction of an innovative and highly flexible, ultra-wideband, Channelizer IP core – the ChannelCore Flex™.
  
  
• Lattice and Flexibilis Announce First FPGA Ethernet Switch IP Cores With HSR (IEC 62439-3) Protocol Support (Monday Jun. 13, 2011)
  Lattice and Flexibilis Oy today announced the immediate availability of the Flexibilis Ethernet Switch (FES) IP cores. The triple speed (10Mbps/100Mbps/1Gbps) FES IP cores operate on Ethernet Layer 2 and can switch with Gigabit forwarding capacity per port. Both Gigabit Fiber optic and Gigabit twisted pair copper Ethernet interfaces are supported.
  
  
• Mixel Achieves First Silicon Success With Its MIPI M-PHY IP (Monday Jun. 13, 2011)
  Mixel’s M-PHY IP supports both TYPE I and TYPE II operation, A and B data rates, and all current and future MIPI M-PHY use-cases, such as DigRF v4, UniProSM 1.4, CSI-3, LLI, and JEDEC’s UFS.
  
  
• Vivante Corporation Dynamic GUI Composition Engine Lowers GPU Power Consumption Up To 5X (Friday Jun. 10, 2011)
  Vivante announced today industry wide adoption of its energy saving display and pixel composition engine by 5 of the top 10 application processor vendors and used in over 30 SoC designs. The composition and GUI engine is a super-fast 2D and pixel processing pipeline that supports up to 8K x 8K resolution.
  
  
• Intilop corporation announces a ‘Game Changing’ record breaking Ultra low latency & highest bandwidth 10G bit TCP offload engine SOC for Xilinx and Altera FPGA families (Thursday Jun. 09, 2011)
  The Mega core integrates 10G TOE, 10G EMAC, CPU Interface, Scalable Streaming FIFO interface. The 10G bit TOE also offers an optional 1G bit EMAC interface. Provides up to 128+ TCP sessions depending upon the FPGA size and still keeps the latency in the 100 ns range.
  
  
• Radically scalable CRISP General Stream Processor solves pitfalls of many-core (Thursday Jun. 09, 2011)
  The CRISP consortium, consisting of Recore Systems (project leader), University of Twente, Atmel, Thales, Tampere University of Technology, and NXP Semiconductors, today presents the final demonstrators of the performant General Stream Processor chip.
  
  
• Alvand Collaborates with GLOBALFOUNDRIES to Provide Analog Mixed-Signal IP for Wireless MIMO Applications (Wednesday Jun. 08, 2011)
  Alvand Technologies today announced that GLOBALFOUNDRIES has chosen to collaborate with Alvand to develop semiconductor IP for the foundry’s 40nm process nodes.
  
  
• Kaben Wireless Announces Programmable JAT (Tuesday Jun. 07, 2011)
  Kaben announced today the pre-release of the KWS430 Jitter Attenuator (JAT), the world's first Programmable JAT IP block for SoC integration.
  
  
• ALLEGRO DVT now targets Wireless Display (WiDi) with its ultra-low latency H.264 IP cores. (Tuesday Jun. 07, 2011)
  Allegro DVT announces the immediate availability of an ultra-low latency version of its H.264/MPEG-4 AVC high-profile, high-definition hardware video encoding IP, suitable for Wireless Display applications.
  
  
• Sonics Announces Innovative Design Environment for Accelerating Network-on-Chip Configuration (Tuesday Jun. 07, 2011)
  Sonics today announced Sonics StudioXE™, an innovative system-level design environment for rapid network-on-chip (NoC) configurability. Sonics StudioXE helps designers accelerate every stage of SoC design —from early architectural exploration to final output, and features an array of robust utilities that help optimize for power, performance and area.
  
  
• Vitesse Gigabit Ethernet IP Cores Enable Proliferation of Ethernet Applications (Monday Jun. 06, 2011)
  Vitesse Semiconductor today introduced a portfolio of Gigabit Ethernet intellectual property (IP) cores for simple and efficient integration of 10/100/1000BASE-T functionality into Ethernet IC solutions for consumer electronics, broadband access, network security, printer, smart grid, storage, and other applications.
  
  
• Sidense First to Offer Antifuse OTP Supporting 1.8V IO in 40nm and 28nm Process Nodes (Monday Jun. 06, 2011)
  Sidense announced that it is the first IP provider to offer antifuse-based memory products supporting 1.8V IO at 40nm and 28nm process nodes.
  
  
• Cadence Extends IP Offering, Collaborates with TSMC via Open Innovation Platform (Monday Jun. 06, 2011)
  Cadence today announced a close collaboration with TSMC that will extend its interface IP offering. The initial outcome of the engineering collaboration will be certified solutions to support the pervasive USB 2.0 and 3.0 standards. The solutions will be supported and sold by Cadence.
  
  
• New AMBA 4 Specification Optimizes Coherency for Heterogeneous Multicore SoCs (Monday Jun. 06, 2011)
  ARM today announced the latest AMBA® 4 interface and protocol specification featuring the AMBA 4 AXI Coherency Extensions (ACE™). Cache coherency is essential in multicore computing applications to efficiently maintain the consistency of data stored in local caches of a shared resource.
  
  
• CAST Complements Popular 8051 Family with New 32-bit Processor Core Partnership (Friday Jun. 03, 2011)
  CAST, Inc. has reached an agreement with Beyond Semiconductor by which CAST will provide Beyond Semiconductor’s BA22 processor core worldwide.
  
  
• Imagination brings long standing experience to successfully deliver DirectX for next generation Windows for SoCs (Thursday Jun. 02, 2011)
  Imagination Technologies is delivering graphics and video IP cores supporting the newest versions of Microsoft DirectX across x86 and ARM based SoCs for the next version of Windows as well as on x86 Windows 7 PCs.
  
  
• Elliptic's NEW security Engine does double duty Between key management and Application processors (Wednesday Jun. 01, 2011)
  Elliptic Technologies has announced the immediate availability of its highly programmable and configurable security accelerator and Hardware Security Module, SPAcc-HSM.
  
  
• X-FAB Releases Ready-to-Use Design IP Blocks for MEMS Accelerometers (Wednesday Jun. 01, 2011)
  X-FAB Silicon Foundries today added ready-to-use design IP blocks for acceleration sensors to its MEMS foundry service offerings. Developed in cooperation with MicroMountains Applications and HSG-IMIT (Institute for Microtechnology and Information Technology of Hahn-Schickard-Gesellschaft), the new IP blocks can be incorporated into customer designs of MEMS capacitive accelerometers covering 2G, 10G and 100G ranges (G = G-force).
  
  
• Xylon Announces new Memory Controller IP core (Wednesday Jun. 01, 2011)
  The new Xylon’s logiMEM_arb memory controller and arbiter IP core allows users to easily connect SDRAM, DDR, DDR2, DDR3, or LPDDR memories to FPGAs. Designed specially for Xilinx Spartan-6 FPGAs, the IP core fully utilizes Xilinx’s MCB embedded block multi-port memory controller hard IP cores and enables the maximum achievable memory bandwidths of up to 6.4 GB/sec.
  
  
• POSEDGE announces Multi-Port Gigabit Ethernet Switch IP with IEEE 1588 &Audio/visual (AV) bridging Support (Wednesday Jun. 01, 2011)
  Posedge has today announced the availability of next generation Multi-Port Gigabit Ethernet Switch Sub-System IP to integrate to ASICs and FPGAs. The Multi-Port Gigabit Ethernet Switch Sub-System IP is based on Wire-speed Secure Packet Processor (WSP) architecture that is scalable from 2-port 10/100 Mbps Switch to 8-Port 10/100/1000 Mbps Switch.
  
  
• EnSilica and Evatronix collaborate on USB connectivity for eSi-RISC processors (Tuesday May. 31, 2011)
  EnSilica has announced a collaboration with Evatronix to offer fully featured eSi-RISC processor SoC solutions incorporating USB 1.1, 2.0 and 3.0 connectivity. The collaboration with Evatronix adds an important building block to EnSilica’s strategy of providing customers with eSi-RISC processor sub-systems complete with integrated peripherals.
  
  
• Chipus announces silicon-proven ultra-low-power PMU IP for portable applications on LFoundry's 150nm technology (Friday May. 27, 2011)
  Chipus Microelectronics announced today the immediate availability of a silicon-proven mixed-signal IP cores performing the functions of a PMU for ultra-low-power applications on LFoundry's advanced 150nm mixed-signal technology.
  
  
• Smart Grid sensitized by Dolphin Integration with high resolution and low-power metering subsystem (Friday May. 27, 2011)
  Dolphin Integration delivers the highest performances in their new subsystems dedicated to Smart Grid applications: sensAFE-PM-SV.09 merges high-resolution ADCs, with up to 20 bits of sensitivity, for 4-channel applications: current, voltage, tampering and auxiliary optimizing calibration.
  
  
• CAST Adds Video and Image Processing Cores to Compression IP Product Line (Friday May. 27, 2011)
  New IP cores for image scaling, video deinterlacing, and graphics acceleration are now available in the Video and Image IP core product line of semiconductor intellectual property (IP) provider CAST, Inc.
  
  
• NXP and Intrinsic-ID demonstrate new security concept on NXP’s security chip against cloning and counterfeiting (Wednesday May. 25, 2011)
  NXP and Intrinsic-ID today announced the availability of a demonstration platform for the deployment of hardware intrinsic security (HIS) solutions based on Physical Unclonable Functions on NXP’s SmartMX security chip platform