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IP / SOC Products News

• Kaben Wireless Announces New IF Digitizer (Monday Apr. 18, 2011)
  Kaben Wireless announced today a new family of ADC products with built-in filtering
  
  
• Arasan Chip Systems Introduces First MIPI RFFE Core (Wednesday Apr. 13, 2011)
  Arasan announced today the introduction of its MIPI RFFE product. The standard is currently a 1.0 document. The Arasan RFFE IP solutions, including IP core, VIP, software drivers and hardware development kit is available immediately for licensing.
  
  
• Cadence Announces Availability of World's First DDR4 IP Solution (Monday Apr. 11, 2011)
  Cadencetoday announced a DDR4 solution. The solution includes hard and soft PHY IP; controller IP; memory models; verification IP; tools and methodologies; and signal integrity reference designs for the package and board.
  
  
• Dolphin Integration announces the availability of StorageWare for facilitating the selection and integration of small memories (Friday Apr. 08, 2011)
  StorageWare™ is a library of synthesizable models (RTL in Verilog-HDL) for storage systems, which combines state-of-the-art performance and productivity improvements in logic design.
  
  
• Digital Core Design releases Revolutionary Quad-Pipelined Ultra High Performance 8051 Microcontroller IP Core (Thursday Apr. 07, 2011)
  Digital Core Design released Revolutionary Quad-Pipelined Ultra High Performance DQ8051 core running Dhrystone 2.1 benchmark program up to 26.62 times faster than the original 80C51 at the same clock frequency.
  
  
• Intrinsic-ID tackles Random Number generation issues and launches iRNG - A true random number GENERATOR - as hard or Soft IP (Thursday Apr. 07, 2011)
  Intrinsic-ID today announced iRNG, a true Random Number Generator delivered as hardware IP (RTL) or embedded software. iRNG utilizes the noise inherently present in uninitialized SRAM to generate random bits at very high speed.
  
  
• RF Engines Ltd (RFEL) adds real time Image Processing of HD video to its range of IP cores and system design work (Wednesday Apr. 06, 2011)
  RF Engines Limited (RFEL) has announced that it is adding Image Processing IP (Intellectual Property) to its extensive range of Digital Signal Processing (DSP) solutions that run on FPGAs.
  
  
• Kilopass' TSMC 28HP HKMG Silicon Results Show Scalability of 2T Antifuse Technology (Tuesday Apr. 05, 2011)
  Kilopass today announced that its first test chip silicon on TSMC 28nm High-K Metal Gate (HKMG) has demonstrated that Kilopass’ 2T antifuse technology is scalable to HKMG. Silicon data shows that existing 2T bit cell performs well on 28HKMG and can scale to 22nm and beyond.
  
  
• Sidense Completes TSMC IP9000 Assessment for Non-Volatile Memory (NVM) Product Families (Tuesday Apr. 05, 2011)
  Sidense announced today that the Company's SLP and ULP OTP product families have met the Assessment requirements of TSMC's rigorous IP9000 program.
  
  
• Dolphin Integration announces a density record for Dual Port Register Files saving up to 30% of area (Friday Apr. 01, 2011)
  The innovative ERIS architecture for Dual Port Register Files is the attractive alternative to conventional Dual Port memory generators at 130 nm. The DpRFolder™ ERIS (2R/2W) allows power and cost reductions, while satisfying the speed constraint of many high-speed applications from high-density consumers and portable devices.
  
  
• Sidense 1T-OTP Memory Available in ON Semiconductor 180 nm Process Technology (Thursday Mar. 31, 2011)
  Sidense and ON Semiconductor have announced that Sidense has ported its 180 nanometer (nm) OTP memory SLP product line to ONC18, ON Semiconductor’s 180 nm digital and mixed-signal technology platform.
  
  
• Synopsys Announces Availability of DesignWare PHY and Embedded Memory IP for TSMC Advanced 28-nanometer Technologies (Wednesday Mar. 30, 2011)
  Synopsys today announced that it has worked with TSMC to develop a broad portfolio of DesignWare® interface PHY IP including SuperSpeed USB 3.0, USB 2.0, HDMI, PCI Express®, DDR and SATA as well as embedded memories for TSMC's 28-nm.
  
  
• MIPS Technologies Unveils Plans for Industry's First 64-Bit Multi-threaded Multiprocessor IP Core Code Named "Prodigy" (Monday Mar. 28, 2011)
  MIPS Technologies today unveiled its plans to offer the industry's first IP core that combines a 64-bit processor architecture with simultaneous multi-threading (SMT) technology.
  
  
• Cadence Releases Industry's First Wide I/O Memory Controller IP Solution (Monday Mar. 28, 2011)
  Cadence Design Systems today announced that it is first to market with a licensable, wide I/O memory controller core, along with an integration environment, that brings PC-like performance to mobile applications like smartphones and tablets.
  
  
• Ocean Logic releases 1080p H.264 encoder and limited decoder with 8-16:1 compressed frame store that requires no off chip DRAM (Monday Mar. 28, 2011)
  Ocean Logic announces the 1080p H.264 Encoder and Limited Decoder IP Cores based on a new, patent pending, Compressed Frame Store (CFS) technology
  
  
• New Tensilica IP Core Targeted to Dataplane and Signal Processing Functions Such as Imaging, Communications and Networking, Boost Data Bandwidth 4X (Monday Mar. 28, 2011)
  Tensilica today announced that it is extending its leadership in IP cores for compute-intensive dataplane and DSP functions such as imaging, video, networking and baseband wired/wireless communications.
  
  
• The new PWM audio Modulator of Dolphin Integration presents high flexibility, up to 95 dB SNR for a DAC (Friday Mar. 25, 2011)
  new PWM audio modulator of Dolphin Integration, sDACS95-SP.01-OL.LB-Titanium, presents numerous high added-value features for advanced fabrication processes: 65 nm, 55 nm and soon at 40 nm.
  
  
• CAST Simplifies PCI Express FPGA Integration with Application-Level Interface Core (Friday Mar. 25, 2011)
  CAST, Inc. has released an IP core that makes it easier to integrate PCI Express in an FPGA-based system. The new PCIEXPAIF IP Core provides a high-level interface between popular system buses like AMBA® AXI4 and the PCI Express hard macro blocks available from FPGA vendors Altera and Xilinx.
  
  
• Elliptic's Family Of Security Protocol Processors Offers Widest Choice In Industry (Wednesday Mar. 23, 2011)
  Elliptic Technologies today unveils a tiered family of Security Protocol Processors (SPP) that represents the broadest portfolio of embedded security solutions for packet processing and general cryptographic operations for all major security protocols (SSL/TLS/DTLS, IPsec, 3GPP/LTE-Advanced, WiMax, MACsec, SRTP, storage and PKI).
  
  
• Intilop announces a record breaking Ultra low latency & highest bandwidth 10G bit TCP offload engine SOC for Altera FPGA family (Monday Mar. 21, 2011)
  Intilop today announced a Mega_IP_SoC for Altera FPGAs that integrates their much heralded flagship 10G bit TCP Offload Engine, their own very low latency 10G EMAC, AMBA APB CPU controller, DDR-2 or DDR-3 controller, mdio controller.
  
  
• Synopsys' Next-Generation DesignWare Data Converter IP Delivers 50 Percent Lower Power with Smaller Area (Monday Mar. 21, 2011)
  Synopsys today announced the release of its next-generation DesignWare® Data Converter IP solutions. Optimized for mobile broadband wireless communication applications such as WiFi, WiMAX, LTE, and digital TV reception, the DesignWare Data Converter IP can reach extremely high sampling rates with excellent dynamic performance, while processing signal bandwidth beyond 100 MHz.
  
  
• Evatronix Adds the SDLL NAND Flash PHY IP to Its Memory Controller IP Portfolio (Monday Mar. 21, 2011)
  Evatronix have announced today the introduction of a SDLL NAND Flash PHY IP that would complement the digital controller IP and provide System-on-Chip developers with a complete solution for High-Speed NAND Flash memories.
  
  
• ArrayComm and CEVA Demonstrate TD-LTE Base Station (Monday Mar. 21, 2011)
  ArrayComm and CEVA today announced the successful demonstration of ArrayComm's BasePort™ TD-LTE base station PHY running on high performance CEVA DSP cores. The demonstration was implemented on Mindspeed's Transcede™ 4000 System-on-Chip and verified by a tier-1 operator.
  
  
• New Analog Bits Display SerDes Reduces Footprint, Power & Cost (Friday Mar. 18, 2011)
  Analog Bits today unveiled an application specific Display SerDes (Serializer/Deserializer) IP that reduces area by up to 25 times, die-costs up to 25% and power consumption by 700mW. The new IP is silicon-proven and available immediately.
  
  
• Evatronix Boosts the Performance of Its ONFi NAND Flash Memory Controller IP (Wednesday Mar. 16, 2011)
  The Evatronix NAND Flash controller will now provide application designers with a set of features aimed at even better support for High-Speed ONFi memories and an up to 64-bit configurable BCH engine for on-the-fly error correction at the highest available frequencies.
  
  
• Aeroflex Gaisler Announces a Fault Tolerant Dual Core Processor for Space Applications (Friday Mar. 11, 2011)
  Aeroflex Gaisler announces today a new fault tolerant processor - the GR712RC. The GR712RC is an implementation of a dual-core LEON3FT SPARC V8 processor using RadSafe technology.
  
  
• GDA (L&T Infotech) Pravega SuperSpeed USB (USB 3.0) IP Receives USB-IF Certification (Thursday Mar. 10, 2011)
  GDA Technologies announced today that its Pravega SuperSpeed USB 3.0 Dual Mode Controller IP successfully passed the USB Implementers Forum (USB-IF) SuperSpeed USB certification for device mode.
  
  
• Open-Silicon Enhances Its Interlaken IP Core for Very High-Speed Chip-to-Chip Serial Interfaces (Thursday Mar. 10, 2011)
  Open-Silicon announced today the availability of an enhanced version of its Interlaken controller IP core. The updated core features fully-configurable SerDes lane mapping between the logical and physical SerDes lanes.
  
  
• Altera Delivers Industry's First Integrated 100G EFEC Solutions for FPGAs (Monday Mar. 07, 2011)
  Altera today announced availability of the industry’s first integrated, enhanced forward error correction (EFEC) IP cores optimized for high performance Stratix ® IV and Stratix V series FPGAs. The EFEC7 and EFEC20 are multi-dimensional IP cores developed by Altera’s Newfoundland Technology Centre (formerly Avalon Microelectronics) and specifically designed for 100G applications such as metro and long-haul optical transport networks (OTN).
  
  
• Mixel and Northwest Logic Deliver a Unified MIPI Platform Supporting Both CSI-2 and DSI (Monday Mar. 07, 2011)
  Mixel and Northwest Logic today announced the availability of their unified MIPI® platform, incorporating the Mixel MIPI D-PHY (Physical Layer) and the Northwest Logic MIPI CSI-2 and DSI Controllers.