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IP / SOC Products News

• Blue Wonder Communications' BWC200 Passed First IOT Tests against ZTE Environment (Tuesday Apr. 20, 2010)
  Blue Wonder Communications has entered into the interoperability testing phase with its recently announced LTE IP product BWC200. During this test session against ZTE’s test environment the BWC200 has successfully passed uplink, downlink and synchronization tests via antenna over the air at up to 20 MHz bandwidth.
  
  
• Customization for market needs comes to a turning point with Dolphin integration Codec Configurator (Friday Apr. 16, 2010)
  Dolphin Integration today reveals its breakthrough configurator for providing fast and safe instances of high performance audio converters from their JAXAUDIO kit of pre-characterized mixed signal blocks.
  
  
• IP Cores, Inc. Announces a New Version of the RSA Public Key Accelerator (Thursday Apr. 15, 2010)
  
  
  
• CoreEL Launches Advanced Video Decoding Solutions (Wednesday Apr. 14, 2010)
  CoreEL Technologies today announced the availability of three new video decoding IP solutions that include, an integrated Broadcast grade H.264 and MPEG-2 HD decoder solution on a single Xilinx® Virtex®-6FPGA., a MPEG-2 4:2:2@HL 1080p60 decoding IP Core working on the high performance Virtex-6 FPGA and a H264/MPEG2 decoding solution working on a low-cost Spartan®-6 FPGA.
  
  
• CAST Offers the First 12-bit JPEG Extended Sequential, DICOM-Compatible IP Core (Tuesday Apr. 13, 2010)
  CAST, Inc. now offers the only encoder core that supports both the Baseline (8-bit) and Extended Sequential (12-bit) modes of the JPEG image compression standard. This plus a fast, compact design make the new JPEG-E-X IP core one of the best available lossy compression encoders for medical imaging, reconnaissance, and other applications where exceptional image detail is required.
  
  
• Virage Logic Extends Non Volatile Memory Leadership; Announces AEON(R) Multi-Time Programmable Parallel NVM Qualified in TSMC 130nm G Process (Tuesday Apr. 13, 2010)
  Virage Logic today expanded its industry leading portfolio of multi-time programmable (MTP) non-volatile memory (NVM) with the qualification of AEON MTP Parallel NVM at TSMC. AEON MTP Parallel NVM now available in 130-nanometer (nm) G process is targeted at analog mixed-signal applications now migrating from 180nm down to 130nm.
  
  
• Virage Logic Announces Availability of a Full Suite of 28nm SiWare Memory Compilers and Rollout of SiWare Logic Libraries for Leading Edge Customers (Tuesday Apr. 13, 2010)
  Virage Logic extends its leadership position by announcing a full suite of 28-nanometer (nm) memory compilers and logic libraries on TSMC’s High-K Metal Gate (28nm HP) process. Following on the early success of their 40nm-node design, two of the company’s longstanding customers have already adopted the 28nm SiWare Memory technology.
  
  
• IP Cores, Inc. Announces Shipment of a New Version of its SHA Family of Hash Cores (Thursday Apr. 08, 2010)
  IP Cores has announced first shipments of a new version of IP cores from its SHA family of cores performing cryptographic hash algorithms. Cryptographic hashes are widely used in the secure communication protocols.
  
  
• OptNgn Releases 264 FFT FPGA Library Elements that are High Performance, Vendor Independent, and Instantly Downloadable (Wednesday Apr. 07, 2010)
  Altera, Xilinx and Mentor Graphics Precision Synthesis users can instantly download, at a cost of $60-$600, streaming FFT IP that will process up to 250 Million complex samples per second.
  
  
• Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY (Wednesday Apr. 07, 2010)
  Synopsys today announced availability of the DesignWare™ DDR multiPHY which is designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area.
  
  
• CEVA Releases SATA3.0 IP for 6Gbps SSD Applications (Wednesday Apr. 07, 2010)
  CEVA today announced the availability of the CEVA-SATA3.0 Device Controller IP. The IP has already been licensed to a leading FLASH memory semiconductor manufacturer for use in their future SSD designs.
  
  
• Novocell Semiconductor Announces the Release of 2nTP; the Industry's First Multi-Time Programmable Antifuse Bit Cell (Wednesday Apr. 07, 2010)
  Novocell today announced the release of 2nTP; the industry’s first multi-time write antifuse technology. 2nTP allows 2n times programming, supporting 2, 4, or 8 times write. For the same number of writes 60% area savings can be achieved versus using multiple cascaded OTP blocks for the same number of writes.
  
  
• Intilop (formerly intelop) releases new fully integrated FPGA-SOC-Platform with TOE, PCI Express and system peripherals that raise the bar in TOE system integration (Thursday Apr. 01, 2010)
  Intilop today announced Xilinx V5 and V6 FPGA based development platforms offering a total system solutions for their TCP offload engine SoC IP. The FPGA embedded development platform integrates various features of TCP/IP protocol in hardware which provide differentiated levels of TCP/IP performance improvement.
  
  
• Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification (Thursday Apr. 01, 2010)
  Synopsys today announced that its DesignWare® SuperSpeed USB (USB 3.0) Solution including Controller and PHY IP successfully passed the USB Implementers Forum (USB-IF) SuperSpeed USB certification.
  
  
• Elliptic Technologies Offers First Security Engine for Multi-Core System-On-Chip Designs (Wednesday Mar. 31, 2010)
  Elliptic Technologies today announced that it has released the latest version of its CLP-600 Security Protocol Accelerator (SPAcc) which now includes the ability to support multiple processor cores from a single hardware security engine.
  
  
• Faraday Launches Its USB 3.0 PHY in UMC 90nm (Tuesday Mar. 30, 2010)
  Faraday Technology today announced the availability of its commercial USB 3.0 physical layer (PHY) at UMC 90nm high-speed (HS) process. With smaller size and lower power consumption than peers', this new component is developed based upon USB 3.0 version 1.0 specification functionally and electrically, achieving the maximum speed of 5.0Gbps.
  
  
• MIPS Technologies and Virage Logic Partner to Offer Optimized Embedded Memory IP (Monday Mar. 29, 2010)
  MIPS and Virage Logic today announced they are teaming to offer optimized embedded memory IP for joint customers. With SRAM memory instances from the Virage Logic ASAP 90nm and SiWare 65GP High Density SRAM compiler families specifically optimized for MIPS32® processors, customers can speed development of complex SoCs targeted for Blu-ray DVD, HDTV, IPTV, set-top box and broadband customer premises equipment (CPE) devices.
  
  
• Dolphin Integration announces the availability of a brand new Front End generator: spRAM Haumea for the 130 nm G process (Friday Mar. 26, 2010)
  Dolphin Integration’s strategy for the 130 nm technological process is to release a Register Bank Panoply for SoC designers with the capability to generate instances from 1 bit up to 512 kbits.
  
  
• Kilopass First to Offer Logic Non-Volatile Memory (NVM) in TSMC 40nm and 45nm Low-Power (LP) Processes (Thursday Mar. 25, 2010)
  Kilopass Technology today announced that its XPM™ embedded one-time programmable (OTP) NVM technology is the first to complete TSMC IP-9000 Level 4 qualification and skew characterization in both the TSMC™ 40nm and 45nm low-power (LP) process technologies.
  
  
• Intilop corporation (formerly intelop) releases a series of new TOE IP solutions that offer the fastest with lowest latency, highest TCP/IP performance and smallest size (Wednesday Mar. 24, 2010)
  Intilop today announced a host of solutions for their TCP offload engine SoC IP.
  
  
• Virage Logic Introduces Industry Leading MIPI D-PHYs and Controllers on 40LP Process (Wednesday Mar. 24, 2010)
  Virage Logic today announced the availability of its SiPro(TM) MIPI Rx D-PHY and MIPI Tx D-PHY as well as CSI Rx (camera serial interface receiver) and DSI Tx (display serial interface transmitter) controllers on the 40LP process node in Q2 of this year which are based on the production proven D-PHYs announced last year.
  
  
• IP Cores, Inc. Ships an AES Encryption Core Supporting the EAX' Encryption Mode of ANSI C12.22 (Wednesday Mar. 24, 2010)
  IP Cores, Inc. has shipped an AES encryption IP core supporting the new EAX’ encryption mode. EAX mode of operation for cryptographic block ciphers implements authenticated encryption with Associated Data (AEAD) algorithm to simultaneously provide both authentication and privacy for the communication link (so called authenticated encryption) via a two-pass operation, with one pass delivering privacy and one authenticity for each message.
  
  
• Dolphin Integration completes their catalog of Standard Cell Libraries with a new stem optimized for low leakage: LL-BTF (Monday Mar. 22, 2010)
  Dolphin Integration’s strategy is to offer to Standard Cell Users a bunch of specialized stems ultimately optimized for one prime criterion. The HD-BTF stem optimized for high density comes first and is already available for major foundries in the 180 nm, 130 nm and 65 nm technological processes.
  
  
• Vitesse's New Forward Error Correction Technology Accelerates Migration to 100G (Monday Mar. 22, 2010)
  Vitesse today announced immediate availability of its enhanced forward error correction (eFEC) technology for implementation in ASICs or FPGAs. Vitesse's new, patented Continuously Interleaved BCH (CI-BCH™) eFEC code offers the highest performing hard decision eFEC available today and is the industry’s only eFEC implementable in single FPGA form at 100G.
  
  
• Intilop (formerly Intelop) corporation's TCP Offload engine IP solution delivers amazing TCP/IP throughput as reported by customers in system level performance testing (Monday Mar. 22, 2010)
  This second generation Customizable Full TCP offload Engine also integrates GEMAC, ARP module, RDMA engines, PLB/405 bus interfaces. It is capable of implementing/accelerating hundreds of simultaneous TCP sessions, delivering 800 % -1500% performance improvement over TCP/IP software implementations.
  
  
• Arteris Announces Support For New ARM AMBA 4 Interconnect Specification (Thursday Mar. 18, 2010)
  Arteris today announced support for the new ARM(R) AMBA(R) 4 specification. Arteris and ARM are working together to ensure interoperability between the AMBA 4 AXI(TM) 4 interface protocol and the Arteris Network on Chip (NoC), and are partnering to deliver optimal system performance for SoC designers using AXI4 protocol-compliant IP together with Arteris NoC interconnect technology.
  
  
• ViaSat Announces New 100G Optical Transport Forward Error Correction (FEC) Products and Digital Signal Processing Services (Wednesday Mar. 17, 2010)
  ViaSat is introducing a family of forward error correction (FEC) products for 100G optical transport. These FEC and digital signal processing (DSP) products, available in either FPGA or ASIC cores, can provide major cost savings over optical compensation techniques, increase optical channel capacity, and extend the range of transmission for optical cables.
  
  
• Innovative Silicon's Z-RAM Technology Meets Low Voltage and Bulk Silicon Requirements of DRAM Memory Manufacturers (Wednesday Mar. 17, 2010)
  Innovative Silicon today announced two major breakthroughs to its Z-RAM technology. First, bit cell operating voltage has been reduced to below one volt (1V), making it the industry’s lowest-voltage FB memory bit cell and the first to be on-par with traditional DRAM voltages. Second, Z-RAM technology is now constructed on bulk silicon – without the requirement for expensive silicon on insulator (SOI) substrates – by using the 3D transistor structures preferred by the major DRAM manufacturers.
  
  
• ARM to Reshape the Smartcard Market with Industry's Smallest and Most Energy-Efficient Securcore SC000 Processor (Tuesday Mar. 16, 2010)
  ARM today announced the launch of the highly compact and energy-efficient ARM® SecurCore™ SC000™ processor, designed specifically for the highest volume smartcard and embedded security applications.
  
  
• Ensphere Solutions Announced the Availability of a High Accuracy Temperature Sensor Intellectual Property (Monday Mar. 15, 2010)
  Ensphere Solutions’ new ESI-P3010 is a power and area optimized IP implemented in mainstream processes such as TSMC 65nm-G and TowerJazz 180 nm. This core consists of a temperature sensor connected to one of the eight inputs of an analog multiplexer.