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IP / SOC Products News

• Rambus Unveils On-chip Noise Monitor to Improve Quality and Reduce Time-to-Market of Complex SoCs (Wednesday Jan. 21, 2015)
  Rambus today announced the addition of an On-chip Noise Monitor to its suite of tools and IP cores. The Noise Monitor is a compact IP block that enables easy and precise noise measurements for both low-power mobile and high-performance server SoCs.
  
  
• Semtech Announces Silicon Proven 25G Ethernet Snowbush IP Compliant with IEEE 802.3bj, CEI-25G, CEI-28G, and the Emerging IEEE 802.3bm and CAUI-4 Standards (Tuesday Jan. 20, 2015)
  Semtech today announced silicon proven results for its Snowbush® IP analog macro operating at 25Gb/s and beyond. The new IP Platform provides lane breakouts in 2x25G (for 50Gb/s), 4x25G (for 100Gb/s) and 8x25G (for 200Gb/s) form factors.
  
  
• Dolphin Integration reveals its unique Regulator offering for IoT markets at 55 nm (Monday Jan. 19, 2015)
  Eager to help System-on-Chip designers get rid of separate power-hungry Power Management ICs (PMIC) in order to ensure their SoC low-power budget, Dolphin Integration promotes their embedding with a disruptive approach.
  
  
• Smart Grid - Power metering: Dolphin Integration achieves range 1/5,000 with class 0.1 on silicon (Thursday Jan. 15, 2015)
  As the leading provider of Virtual Components for high-resolution converters, Dolphin Integration announces proven state-of-the-art Silicon IP for Fabless and SoC integrators targeting the growing Smart Grid related markets, such as Utility Billing meters or Smart plugs.
  
  
• Mobiveil, Inc. and M31 Technology Announce A Compliant PCI Express PHY and Controller Solution (Wednesday Jan. 14, 2015)
  Mobiveil together with M31 Technology jointly announced completion of a compliant PCI Express® (PCIe®) 2.0 IP solution for designers building system on chip solutions (SOC) for the fast growing mobile and consumer markets in Asia.
  
  
• PLDA and M31 Technology Combine PCIe 3.0 Controller and PHY IP for a Complete, Reliable ASIC Design Solution (Tuesday Jan. 13, 2015)
  The combined solution -- PLDA’s PCIe 3.0 controller in Gen2 XpressRICH3 with M31 Technology’s PHY IP – received certification from PCI-SIG which was validated on PLDA Kintex-7-based platform XpressK7 and M31 Technology’s daughter card. The complete solution is optimized for storage applications.
  
  
• Latest Tensilica Processors Deliver Up to 75% Memory Power and Area Savings (Monday Jan. 12, 2015)
  Cadence today announced the 11th generation of the Tensilica® Xtensa® processors. The new Xtensa LX6 and Xtensa 11 processors enable users to create innovative custom processor instruction sets with up to 25 percent less processor logic power consumption and up to 75 percent better local memory area and power efficiency.
  
  
• Arasan announces Total IP Solution for MIPI SoundWire (Thursday Jan. 08, 2015)
  Arasan brings expertise in serial audio and over one hundred design wins with MIPI® SLIMbusSM to the MIPI SoundWire specification.
  
  
• Cadence Announces Fourth Generation Tensilica HiFi DSP Architecture (Tuesday Jan. 06, 2015)
  Cadence today announced the Cadence® Tensilica® HiFi 4 audio/voice DSP IP core for SoC designs, which offers the industry’s highest performance licensable digital signal processing (DSP) core for 32-bit audio/voice processing.
  
  
• Creonic Unveils 100 Gbit/s IEEE 802.3bj Reed-Solomon FEC IP Cores (Monday Jan. 05, 2015)
  
  
  
• Mindtree Becomes the World's First Bluetooth Smart 4.2 IP Provider (Thursday Dec. 18, 2014)
  Mindtree today announced the qualification of its Bluetooth Smart IP for version 4.2. Mindtree has been a leading provider of Bluetooth Intellectual Property solutions over the last 15 years and this qualification is the most recent in its long list of Bluetooth IPs.
  
  
• Mobiveil Announces Fully Compliant RapidIO 10xN (Gen 3) Digital Controller IP Supporting Multi-Channel DMA, Data Message and Data Streaming at 40Gbps (Tuesday Dec. 16, 2014)
  Mobiveil today announced a fully compliant RapidIO 10xN (Gen 3) Digital controller IP supporting multi-channel DMA, data message and data streaming at 40Gbps. Besides supporting ASIC and standard cell design flows for designers building wireless network infrastructure and aerospace solutions, where RapidIO has long been the interface of choice, Mobiveil will be targeting ARM® based server and heterogeneous compute (HPC) platforms with this release.
  
  
• Crossbar Unveils Another Breakthrough Innovation Behind its Ultra-High Density 3D RRAM Solutions (Monday Dec. 15, 2014)
  Demonstrates Industry’s First Patented Field Assisted Superlinear Threshold Selector Device to Overcome Sneak Path Current Problem in 3D Crosspoint RRAM Arrays
  
  
• VLSI Plus Announces Multiplexing CSI2 Transceiver IP core (Thursday Dec. 11, 2014)
  VLSI Plus today announced the availability of the CSI2-MUX-A1-F – a MIPI® CSI2 transceiver, connecting to up to 4 CSI2 camera inputs, and outputting a multiplexed CSI2 stream with 4 data lanes, at up to 1.5Gbps per lane.
  
  
• IDT Launches RapidIO 40-100 Gbps Interface Portfolio, Reducing Latency and Boosting Bandwidth for Communications and Computing (Wednesday Dec. 10, 2014)
  IDT today announced the launch of a RapidIO® 40-100 Gbps interface product portfolio, developed to lower latency while improving bandwidth for high-performance computing (HPC), wireless, analytics and embedded applications.
  
  
• Allegro DVT unveils its hardware dual-format (HEVC/H.265 and AVC/H.264) encoder IP (Monday Dec. 08, 2014)
  Allegro DVT announces its dual-format encoder IP core, implementing the two mainstream video compression formats: HEVC/H.265 and AVC/H.264. With this new IP, Allegro DVT enlarges its video encoding IP offering with the first hardware encoder supporting both standards.
  
  
• Dolphin Integration, provider of IP components for Smartcard applications with focus on security and low power (Monday Dec. 08, 2014)
  Dolphin Integration offers secured microcontroller configurations, embedding custom sets of counter-measures, tailored to each user request. Moreover, Dolphin Integration is THE provider of low-power optimized Silicon IP components with a wide offering in eFlash processes at 90 nm and 55 nm.
  
  
• Arasan Chip Systems Announces Successful InterOp Testing of SD 4.1 and UHS-II Total IP Solution (Thursday Dec. 04, 2014)
  Arasan announced results of successful compatibility testing of Arasan’s Total SD 4.1 IP Solution, including Host interface, software stack and UHS-II interface card at the SDA InterOp in Tokyo, November 2014.
  
  
• D6811E - 4 times faster architecture for HC11 (Tuesday Dec. 02, 2014)
  Digital Core Design introduced the D6811E IP Core. It aims at IoT sensors and beacons, but thanks to its binary compatibility with the Motorola’s 68HC11, it can be implemented in barcode readers, hotel card key writers, robotics, and various embedded systems.
  
  
• IPrium releases DVB-CID Demodulator (Tuesday Dec. 02, 2014)
  FPGA intellectual property (IP) provider IPrium LLC today announced that it has expanded its family of Demodulator IP products with a new DVB-CID Demodulator IP Core for the ETSI Carrier identification (CarrierID) standard.
  
  
• Dolphin Integration raises its status of one-stop-shop for IoT devices (Monday Dec. 01, 2014)
  Going beyond providing a set of low-power optimized Silicon IP components for the needs of IoT devices, Dolphin Integration addresses the challenge of assembling and verifying the most efficient power management architectures, delivered with the relevant advanced views to enable consistent verifications at SoC level. Finally a number of activity control units for the detailed and safe management of dual voltage and frequency stepping.
  
  
• Sercos IP Core Available for Altera Cyclone V FPGAs and SoCs (Thursday Nov. 27, 2014)
  Sercos International, provider of the Sercos® automation bus, announced today the availability of the Sercos III IP Core for Altera's low-cost, low-power Cyclone® V devices. The IP core is available for Sercos III master and slave controllers (SERCON100M/S). It includes all hardware functions, such as timing, synchronization and processing of cyclic and non-cyclic data on the basis of two integrated Ethernet MACs
  
  
• Dolphin Integration reveals the standard power kit library DELTA to ease the deployment of an optimal power management network into a SoC (Monday Nov. 24, 2014)
  To overcome the power challenge, Power Management Networks (PMNet) are becoming more and more complex. Making the right choices for embedding PMNets into System-on-Chips (SoC) might result in tricky issues for the integrator.
  
  
• PLDA Introduces XpressRICH4: The PCIe 4.0 Controller of Choice When Performance Matters (Wednesday Nov. 19, 2014)
  PLDA has introduced XpressRICH4, a highly configurable PCIe 4.0 interface soft IP designed for ASIC implementations and seamless FPGA prototyping implementations. Building on PLDA’s long history of numerous tape-outs in leading-edge process technologies, XpressRICH4 includes advanced features such as single root I/O virtualization (SR-IOV) and data-path protection.
  
  
• Elliptic Technologies Unveils Future-Proof Secure Hardware Root of Trust Technology (Wednesday Nov. 19, 2014)
  Elliptic Technologies today unveiled tRoot™, its future-proof secure hardware root of trust technology targeting the increasing security challenges in the Internet of Things (IoT).
  
  
• Credo Tapes Out Industry-leading Serdes IP on 16-nm FinFET+ Process (Wednesday Nov. 19, 2014)
  Credo Semiconductor today announced it has successfully taped out its popular 28G and 56G SerDes transceiver IP on TSMC's 16-nm FinFET+ (FF+) process. By successfully porting its IP to this advanced processing node, Credo enables ASSP, ASIC and SoC designers to deliver solutions that address the growing performance and bandwidth demands of next-generation 100G and 400G networks.
  
  
• Synopsys Expands IP Accelerated Initiative with New DesignWare IP Prototyping Kits for 10 Interface Protocols (Wednesday Nov. 19, 2014)
  Synopsys today expanded its IP Accelerated initiative with new DesignWare® IP Prototyping Kits for 10 interface protocols, including USB 3.0, SSIC, PCI Express 2.0, PCI Express 3.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI 2.0 and JEDEC UFS.
  
  
• Open-Silicon Announces Availability of World's First HMC 2.0 Memory Controller IP (Wednesday Nov. 19, 2014)
  Open-Silicon today announced a comprehensive Hybrid Memory Cube (HMC) 2.0 controller solution as licensable Intellectual Property (IP) that will enable SoC designers to take immediate advantage of the performance gains afforded by the emerging memory standard.
  
  
• Rambus and Mobiveil Partner to Bring Pre-Validated Solution to Chip Makers, Delivering Memory Flexibility and Accelerated Time-to-Market (Wednesday Nov. 19, 2014)
  Rambus Inc. and Mobiveil today announced they have validated interoperability of the Rambus R+™ DDR4 Multi-modal PHY with the Mobiveil Universal Multiport Memory Controller (UMMC) Core for JEDEC standard DDR4/3 and LPDDR3/2 operation.
  
  
• eMemory Offers IP Industry-Leading Hybrid MTP SIP (Wednesday Nov. 19, 2014)
  Targeting the market demand of integrated IC, eMemory announced today the availability of Hybrid MTP, a leading integrated Multiple Times Programmable (MTP) Silicon Intellectual Property (SIP). Base on the applications, clients can select the suitable OTP solution (NeoBit) and MTP solution (NeoMTP) from eMemory’s diverse SIP portfolio, and customize the composition of OTP and MTP in the Hybrid MTP.