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IP / SOC Products News

• Dolphin Integration announces the availability of the new generation of SpRAM generator at 90 nm and 55 nm eFlash (Monday Feb. 10, 2014)
  The high density and low power architecture RHEA for SpRAM is now available in the eFlash process variant for the 90 nm and 55 nm nodes. This SpRAM is designed to reach the highest density and gains from 10 to 20% versus alternative solutions in 90 nm and 55 nm.
  
  
• eMemory Expands NeoFlash's Industrial Applications (Monday Feb. 10, 2014)
  eMemory today announced an technology advancement with Vanguard International Semiconductor Corporation (VIS) of 0.16um high-voltage process embedded flash NeoFlash silicon intellectual property (SIP).
  
  
• IP Cores, Inc. Announces Shipments of the FPGA Version of Its 100 Gbps MACsec IP Cores (Tuesday Feb. 04, 2014)
  IP Cores has announced shipments of an FPGA version of its MSP10 core that supports line-speed MACsec encryption and decryption for the 100 Gbps Ethernet solutions.
  
  
• Digital Core Design Introduces EEPROM IP Core with configurable SPI parameters (Monday Feb. 03, 2014)
  Digital Core Design introduced its latest solution – DEEPROM. It performs communication and exchanges data between ex-ternal serial EEPROM Memory and CPU’s RAM memory interface. Moreover, DCD’s IP Core DEEPROM implements configurable SPI parameters like serial clock prescaler, SPI mode, CS hold/setup.
  
  
• Arasan Chip Systems Announces MIPI D-PHY Module for Prototype Development (Thursday Jan. 30, 2014)
  Arasan announced today the availability of a MIPI D-PHY module for prototype development. The D-PHY prototype module enables development, validation, testing and launching products with MIPI camera (CSI-2) and display (DSI) interfaces, in the shortest possible time frame.
  
  
• Cadence DDR4 PHY IP Achieves 2667 Mbps Performance - Fastest in the Industry (Wednesday Jan. 29, 2014)
  
  
  
• Precision AFE Current to Voltage Converter Now Available for Analog ASIC Integration (Wednesday Jan. 29, 2014)
  JVD Inc. announced today the availability of a critical Analog Front End IP block designed for conditioning signals from sensors where the generic information about the phenomenon being detected, whether light or other physical or chemical or electromechanical apparatus, passes the first electrical conversion as a current.
  
  
• Synopsys Announces Immediate Availability of Multiprotocol DesignWare Enterprise 12G PHY IP (Tuesday Jan. 28, 2014)
  Synopsys today announced the availability of its multiprotocol DesignWare® Enterprise 12G PHY IP to reduce power consumption and increase performance in a broad range of high-end networking and computing applications.
  
  
• Sonics Introduces Second Generation Asynchronous Bridge IP For Complex, Multi-Domain Soc Designs (Tuesday Jan. 28, 2014)
  SonicsExpress includes a number of new features and capabilities that support dynamic voltage and frequency scaling (DVFS) for system-on-chip (SoC) designs that incorporate multiple power and clocking domains. SonicsExpress delivers highly efficient clock domain crossings for dataflow sockets while minimizing signal and gate count.
  
  
• Fastest-Running 8051 Microcontroller IP Core Now Available from CAST (Tuesday Jan. 28, 2014)
  An 8051-compatible microcontroller core with 26.85 times the performance per MHz of the original 8051 chip is now available from semiconductor intellectual property provider CAST, Inc.
  
  
• First CAN FD Bus Controller IP Core for ASICs & FPGAs Available Now from CAST (Wednesday Jan. 22, 2014)
  CAST is now shipping what it believes is the first available CAN Bus Controller soft IP core that supports the recent CAN Flexible Data specification. Sourced from Fraunhofer IPMS, the revised product adds FD support to the CAN 2.0 controller core CAST has carried for several years.
  
  
• Dolphin Integration announces groundbreaking regulators for multi-mode optimization of consumption (Monday Jan. 20, 2014)
  Dolphin Integration today announced the Retention Alternating Regulator (RAR) as a fully integrated, secure and power-efficient solution for supplying loads requiring multi-mode optimization, with a low Bill-of-Material.
  
  
• Xylon announces new version of the Bayer Sensor Decoder IP core (Friday Jan. 17, 2014)
  Xylon announces new version of the logiBAYER Color Camera Sensor Bayer Decoder IP core with support for ultra high resolutions up to 4096x4096 (including 4K2K). It is designed for video frame grabbing from video cameras and other video sources in high-performance embedded real-time video and image processing applications.
  
  
• Semtech's PCI Express 3.0 PHY IP Platform is Fully Compliant and Included on PCI-SIG Integrators List (Wednesday Jan. 15, 2014)
  Semtech today announced its PCI Express® (PCIe®) 3.0 PHY IP, part of the Snowbush® IP platform, successfully completed the rigorous testing of the PCI-SIG® and is now on the PCIe 3.0 Integrators List.
  
  
• oViCs Introduces 4Kp120 HEVC/H.265 Decoder (Wednesday Jan. 15, 2014)
  oViCs today introduced ViC-1, the world's highest performance and high efficiency 4Kp120 HEVC/H.265 decoder supporting Main, Main-10, and Main Still Picture Profiles up to Level 5.2, High Tier.
  
  
• PLDA's XpressRICH3-AXI PCI Express 3.0 IP with AMBA AXI Support Passes PCI-SIG PCIe 3.0 Compliance Testing (Tuesday Jan. 14, 2014)
  PLDA today announced that its XpressRICH3-AXI™ PCI Express® (PCIe®) 3.0 solution with AMBA AXI support, passed all Gold and Interoperability tests performed by the PCI-SIG® committee during its most recent workshop in December 2013.
  
  
• Digital Core Design Introduces DSMART IP Core for smart card reader apps (Thursday Jan. 09, 2014)
  Digital Core Design introduced its latest solution, the DSMART. Based on ISO 7816-3/EMV4.2 requirements, it implements the hardware support for both T0 character oriented protocol and T1 block oriented protocol. Ipso facto, the Core is an answer to growing demand for solutions supporting the IC chip systems, visible in the previous months.
  
  
• INSIDE Secure First to Market with Secure Element IP Solution (Wednesday Jan. 08, 2014)
  INSIDE Secure today introduced a new approach to embedding a robust security platform in mobile devices to fortify and protect them against system integrity attacks. The first of its kind, the power-optimized INSIDE Secure VaultIP solution provides a set of certification-ready hardware IP modules that chip makers can use to quickly and cost effectively embed hardware secure elements in their mobile designs, either stand-alone or for use in an ARM TrustZone® architecture.
  
  
• Vivante GC7000 GPU IP Core with Geometry and Tessellation Shaders Brings 4K Ultra HD Gaming to Any Screen (Tuesday Jan. 07, 2014)
  Vivante today announced the release of its next generation GC7000 series graphics IP cores based on Vega technology enhanced with next generation geometry and tessellation shaders. The advances will bring breakthrough performance, quality, and photo-realistic 4K rendering to any mobile or TV screen, boosting the 3D experience in games, apps, and GPU accelerated web browsers.
  
  
• CEVA Releases Architecture Enhancements for the CEVA-TeakLite-4 DSP Aimed at Further Improving Power Efficiency and Performance (Tuesday Jan. 07, 2014)
  CEVA, Inc. (NASDAQ: CEVA), the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today announced the release of the CEVA-TeakLite-4 v2 DSP architecture, further boosting the performance and lowering the power consumption of the world’s most popular DSP architecture for audio/voice applications.
  
  
• Imagination's new generation PowerVR Series6XT architecture delivers up to 50% higher performance and advanced power management (Monday Jan. 06, 2014)
  Imagination Technologies unveils the next generation of its highly successful PowerVR Rogue graphics processing (GPU) architecture that drives performance to new levels while reducing power consumption even further through advanced PowerGearing mechanisms. The new PowerVR Series6XT Rogue architecture builds on the groundbreaking Series6 architecture that consumes the lowest memory bandwidth in the industry while delivering the best performance per mm2 and per mW.
  
  
• InterDigital and Blu Wireless Advance Millimeter Wave Technology for Backhaul Between Small-Cell Base Stations (Friday Jan. 03, 2014)
  InterDigital and Blu Wireless Technology today announced the successful completion of a first phase of collaborative development to explore millimeter wave solutions for small cell base stations and access points.
  
  
• GUC and M31 Technology Bundle USB 3.0 Peripheral Device Controller and PHY IP (Monday Dec. 30, 2013)
  GUC and M31 Technology today unveiled a combination USB 3.0 IP that bundles GUC’s Peripheral Device Controller IP and M31 Technology’s PHY IP that is now available on 65/55nm, 40nm, and 28nm process technologies.
  
  
• Sidense 1T-OTP Memory Macros meet JEDEC Accelerated Testing Qualifications at Two TSMC 28nm Process Nodes (Thursday Dec. 26, 2013)
  Sidense today announced that its SHF Non-Volatile Memory (NVM) macros have met stringent JEDEC accelerated testing requirements for TSMC’s 28HPM and 28HPL process nodes.
  
  
• Blu Wireless combines Imagination's MIPS Aptiv CPUs in groundbreaking 60GHz System IP for WiGig and backhaul markets (Tuesday Dec. 17, 2013)
  Imagination Technologies and Blu Wireless Technology are sharing details of Blu Wireless’ new HYDRA baseband technology for efficient multi-gigabit wireless processing. The ground-breaking technology leverages multiple MIPS Aptiv processors together with HYDRA vector DSP technology in a unique heterogeneous multiprocessing architecture targeting the burgeoning 60GHz space.
  
  
• MagnaCom Demonstrates a 20 year Leap in Digital Communications (Tuesday Dec. 17, 2013)
  MagnaCom has invented a new revolutionary technology, which can save spectrum and power, while increasing bandwidth, speed and distance, for state-of-the-art wired and wireless devices. WAM delivers those benefits while maintaining 100% backward compatibility with the legacy devices in use today.
  
  
• MagnaChip and eMemory to offer 0.18um EEPROM IP (Monday Dec. 16, 2013)
  MagnaChip Semiconductor, a Korea-based designer and manufacturer of analog and mixed signal semiconductor products, today announced that it has completed qualification of 0.18um EEPROM intellectual property (IP) developed in partnership with eMemory Technology, Inc., a leading Taiwanese non-volatile memory (NVM) IP provider.
  
  
• Dolphin Integration launches new AHB compliant Cache controller to meet growing demand for both energy efficient and faster SoC with NVM (Monday Dec. 16, 2013)
  
  
  
• Arasan Chip Systems Announces 64-bit Compatible Interface IP for Mobile Storage (Tuesday Dec. 10, 2013)
  Arasan announced today the availability of compatible mobile storage interfaces for 64-bit processors, using system host interfaces AHB, AXI or OCP. Compatible standards include: SD 3.0, SD 4.0, SDIO 3.0, SDIO 4.0, eMMC 4.51, eMMC 5.0, ONFI 3.2, and UFS 2.0.
  
  
• Synopsys Demonstrates Industry's First SuperSpeed USB 10 Gbps Platform-to-Platform Host-Device IP Data Transfer (Tuesday Dec. 10, 2013)
  Synopsys today announced its successful demonstration of the industry's first SuperSpeed USB 10 Gbps (USB 3.1) platform-to-platform Host-Device IP data transfer.